package/boot/uboot-sunxi/patches/4017-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch

   1 From 8cd51196fec0b7544cb5842dac9f7209542a6a61 Mon Sep 17 00:00:00 2001
   2 From: Andre Przywara <andre.przywara@arm.com>
   3 Date: Fri, 21 Jul 2023 14:45:57 +0100
   4 Subject: [PATCH 4017/4044] sunxi: clock: D1/R528: Enable PLL LDO during PLL1
   5  setup
   6
   7 The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL.
   8 Just enable that when we program that PLL.
   9
  10 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
  11 ---
  12  arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h |  1 +
  13  arch/arm/mach-sunxi/clock_sun50i_h6.c             | 12 +++++++-----
  14  2 files changed, 8 insertions(+), 5 deletions(-)
  15
  16 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
  17 index 37df4410ea..9895c2c220 100644
  18 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
  19 +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
  20 @@ -228,6 +228,7 @@ struct sunxi_ccm_reg {
  21
  22  /* pll1 bit field */
  23  #define CCM_PLL1_CTRL_EN               BIT(31)
  24 +#define CCM_PLL1_LDO_EN                        BIT(30)
  25  #define CCM_PLL1_LOCK_EN               BIT(29)
  26  #define CCM_PLL1_LOCK                  BIT(28)
  27  #define CCM_PLL1_OUT_EN                        BIT(27)
  28 diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
  29 index 7926394cf7..90110eab10 100644
  30 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
  31 +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
  32 @@ -86,11 +86,13 @@ void clock_set_pll1(unsigned int clk)
  33         writel(val, &ccm->cpu_axi_cfg);
  34
  35         /* clk = 24*n/p, p is ignored if clock is >288MHz */
  36 -       writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
  37 -#ifdef CONFIG_MACH_SUN50I_H616
  38 -              CCM_PLL1_OUT_EN |
  39 -#endif
  40 -              CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg);
  41 +       val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2;
  42 +       val |= CCM_PLL1_CTRL_N(clk / 24000000);
  43 +       if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
  44 +              val |= CCM_PLL1_OUT_EN;
  45 +       if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
  46 +              val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN;
  47 +       writel(val, &ccm->pll1_cfg);
  48         while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
  49
  50         /* Switch CPU to PLL1 */
  51 --
  52 2.20.1
  53