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uboot-sunxi: t113: refresh patches to fix clock issues
[openwrt/staging/wigyori.git] / package / boot / uboot-sunxi / patches / 4016-clk-sunxi-Add-support-for-the-D1-CCU.patch
1 From 716a59d3d21ebb997f345b28b972d8f6e627fe34 Mon Sep 17 00:00:00 2001
2 From: Samuel Holland <samuel@sholland.org>
3 Date: Fri, 21 Jul 2023 14:45:56 +0100
4 Subject: [PATCH 4016/4044] clk: sunxi: Add support for the D1 CCU
5
6 Since the D1 CCU binding is defined, we can add support for its
7 gates/resets, following the pattern of the existing drivers.
8
9 Signed-off-by: Samuel Holland <samuel@sholland.org>
10 Reviewed-by: Andre Przywara <andre.przywara@arm.com>
11 Acked-by: Sean Anderson <seanga2@gmail.com>
12 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
13 ---
14 drivers/clk/sunxi/Kconfig | 6 +
15 drivers/clk/sunxi/Makefile | 1 +
16 drivers/clk/sunxi/clk_d1.c | 84 ++++++++++++
17 drivers/clk/sunxi/clk_sunxi.c | 5 +
18 include/dt-bindings/clock/sun20i-d1-ccu.h | 158 ++++++++++++++++++++++
19 include/dt-bindings/reset/sun20i-d1-ccu.h | 79 +++++++++++
20 6 files changed, 333 insertions(+)
21 create mode 100644 drivers/clk/sunxi/clk_d1.c
22 create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h
23 create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h
24
25 diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
26 index bf11fad6ee..f65e482ba4 100644
27 --- a/drivers/clk/sunxi/Kconfig
28 +++ b/drivers/clk/sunxi/Kconfig
29 @@ -87,6 +87,12 @@ config CLK_SUN8I_H3
30 This enables common clock driver support for platforms based
31 on Allwinner H3/H5 SoC.
32
33 +config CLK_SUN20I_D1
34 + bool "Clock driver for Allwinner D1"
35 + help
36 + This enables common clock driver support for platforms based
37 + on Allwinner D1 SoC.
38 +
39 config CLK_SUN50I_H6
40 bool "Clock driver for Allwinner H6"
41 default MACH_SUN50I_H6
42 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
43 index 895da02ebe..90a277489d 100644
44 --- a/drivers/clk/sunxi/Makefile
45 +++ b/drivers/clk/sunxi/Makefile
46 @@ -19,6 +19,7 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
47 obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
48 obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
49 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
50 +obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o
51 obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
52 obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
53 obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
54 diff --git a/drivers/clk/sunxi/clk_d1.c b/drivers/clk/sunxi/clk_d1.c
55 new file mode 100644
56 index 0000000000..9dae761de8
57 --- /dev/null
58 +++ b/drivers/clk/sunxi/clk_d1.c
59 @@ -0,0 +1,84 @@
60 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
61 +/*
62 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
63 + */
64 +
65 +#include <common.h>
66 +#include <clk-uclass.h>
67 +#include <dm.h>
68 +#include <errno.h>
69 +#include <clk/sunxi.h>
70 +#include <dt-bindings/clock/sun20i-d1-ccu.h>
71 +#include <dt-bindings/reset/sun20i-d1-ccu.h>
72 +#include <linux/bitops.h>
73 +
74 +static struct ccu_clk_gate d1_gates[] = {
75 + [CLK_APB0] = GATE_DUMMY,
76 +
77 + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
78 + [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
79 + [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
80 + [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
81 + [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
82 + [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
83 + [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
84 + [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
85 + [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
86 + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
87 + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
88 + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
89 + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
90 + [CLK_SPI0] = GATE(0x940, BIT(31)),
91 + [CLK_SPI1] = GATE(0x944, BIT(31)),
92 + [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
93 + [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
94 +
95 + [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
96 +
97 + [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
98 + [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
99 + [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
100 + [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
101 + [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
102 + [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
103 + [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
104 + [CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)),
105 +
106 + [CLK_RISCV] = GATE(0xd04, BIT(31)),
107 +};
108 +
109 +static struct ccu_reset d1_resets[] = {
110 + [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
111 + [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
112 + [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
113 + [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
114 + [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
115 + [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
116 + [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
117 + [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
118 + [RST_BUS_UART5] = RESET(0x90c, BIT(21)),
119 + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
120 + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
121 + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
122 + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
123 + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
124 + [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
125 +
126 + [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
127 +
128 + [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
129 + [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
130 + [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
131 + [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
132 + [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
133 + [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
134 + [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
135 + [RST_BUS_LRADC] = RESET(0xa9c, BIT(16)),
136 +};
137 +
138 +const struct ccu_desc d1_ccu_desc = {
139 + .gates = d1_gates,
140 + .resets = d1_resets,
141 + .num_gates = ARRAY_SIZE(d1_gates),
142 + .num_resets = ARRAY_SIZE(d1_resets),
143 +};
144 diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
145 index ec02a2d037..a0011a35d9 100644
146 --- a/drivers/clk/sunxi/clk_sunxi.c
147 +++ b/drivers/clk/sunxi/clk_sunxi.c
148 @@ -118,6 +118,7 @@ extern const struct ccu_desc a64_ccu_desc;
149 extern const struct ccu_desc a80_ccu_desc;
150 extern const struct ccu_desc a80_mmc_clk_desc;
151 extern const struct ccu_desc a83t_ccu_desc;
152 +extern const struct ccu_desc d1_ccu_desc;
153 extern const struct ccu_desc f1c100s_ccu_desc;
154 extern const struct ccu_desc h3_ccu_desc;
155 extern const struct ccu_desc h6_ccu_desc;
156 @@ -214,6 +215,10 @@ static const struct udevice_id sunxi_clk_ids[] = {
157 #ifdef CONFIG_CLK_SUNIV_F1C100S
158 { .compatible = "allwinner,suniv-f1c100s-ccu",
159 .data = (ulong)&f1c100s_ccu_desc },
160 +#endif
161 +#ifdef CONFIG_CLK_SUN20I_D1
162 + { .compatible = "allwinner,sun20i-d1-ccu",
163 + .data = (ulong)&d1_ccu_desc },
164 #endif
165 { }
166 };
167 diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h
168 new file mode 100644
169 index 0000000000..e143b99297
170 --- /dev/null
171 +++ b/include/dt-bindings/clock/sun20i-d1-ccu.h
172 @@ -0,0 +1,158 @@
173 +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
174 +/*
175 + * Copyright (C) 2020 huangzhenwei@allwinnertech.com
176 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
177 + */
178 +
179 +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
180 +#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
181 +
182 +#define CLK_PLL_CPUX 0
183 +#define CLK_PLL_DDR0 1
184 +#define CLK_PLL_PERIPH0_4X 2
185 +#define CLK_PLL_PERIPH0_2X 3
186 +#define CLK_PLL_PERIPH0_800M 4
187 +#define CLK_PLL_PERIPH0 5
188 +#define CLK_PLL_PERIPH0_DIV3 6
189 +#define CLK_PLL_VIDEO0_4X 7
190 +#define CLK_PLL_VIDEO0_2X 8
191 +#define CLK_PLL_VIDEO0 9
192 +#define CLK_PLL_VIDEO1_4X 10
193 +#define CLK_PLL_VIDEO1_2X 11
194 +#define CLK_PLL_VIDEO1 12
195 +#define CLK_PLL_VE 13
196 +#define CLK_PLL_AUDIO0_4X 14
197 +#define CLK_PLL_AUDIO0_2X 15
198 +#define CLK_PLL_AUDIO0 16
199 +#define CLK_PLL_AUDIO1 17
200 +#define CLK_PLL_AUDIO1_DIV2 18
201 +#define CLK_PLL_AUDIO1_DIV5 19
202 +#define CLK_CPUX 20
203 +#define CLK_CPUX_AXI 21
204 +#define CLK_CPUX_APB 22
205 +#define CLK_PSI_AHB 23
206 +#define CLK_APB0 24
207 +#define CLK_APB1 25
208 +#define CLK_MBUS 26
209 +#define CLK_DE 27
210 +#define CLK_BUS_DE 28
211 +#define CLK_DI 29
212 +#define CLK_BUS_DI 30
213 +#define CLK_G2D 31
214 +#define CLK_BUS_G2D 32
215 +#define CLK_CE 33
216 +#define CLK_BUS_CE 34
217 +#define CLK_VE 35
218 +#define CLK_BUS_VE 36
219 +#define CLK_BUS_DMA 37
220 +#define CLK_BUS_MSGBOX0 38
221 +#define CLK_BUS_MSGBOX1 39
222 +#define CLK_BUS_MSGBOX2 40
223 +#define CLK_BUS_SPINLOCK 41
224 +#define CLK_BUS_HSTIMER 42
225 +#define CLK_AVS 43
226 +#define CLK_BUS_DBG 44
227 +#define CLK_BUS_PWM 45
228 +#define CLK_BUS_IOMMU 46
229 +#define CLK_DRAM 47
230 +#define CLK_MBUS_DMA 48
231 +#define CLK_MBUS_VE 49
232 +#define CLK_MBUS_CE 50
233 +#define CLK_MBUS_TVIN 51
234 +#define CLK_MBUS_CSI 52
235 +#define CLK_MBUS_G2D 53
236 +#define CLK_MBUS_RISCV 54
237 +#define CLK_BUS_DRAM 55
238 +#define CLK_MMC0 56
239 +#define CLK_MMC1 57
240 +#define CLK_MMC2 58
241 +#define CLK_BUS_MMC0 59
242 +#define CLK_BUS_MMC1 60
243 +#define CLK_BUS_MMC2 61
244 +#define CLK_BUS_UART0 62
245 +#define CLK_BUS_UART1 63
246 +#define CLK_BUS_UART2 64
247 +#define CLK_BUS_UART3 65
248 +#define CLK_BUS_UART4 66
249 +#define CLK_BUS_UART5 67
250 +#define CLK_BUS_I2C0 68
251 +#define CLK_BUS_I2C1 69
252 +#define CLK_BUS_I2C2 70
253 +#define CLK_BUS_I2C3 71
254 +#define CLK_SPI0 72
255 +#define CLK_SPI1 73
256 +#define CLK_BUS_SPI0 74
257 +#define CLK_BUS_SPI1 75
258 +#define CLK_EMAC_25M 76
259 +#define CLK_BUS_EMAC 77
260 +#define CLK_IR_TX 78
261 +#define CLK_BUS_IR_TX 79
262 +#define CLK_BUS_GPADC 80
263 +#define CLK_BUS_THS 81
264 +#define CLK_I2S0 82
265 +#define CLK_I2S1 83
266 +#define CLK_I2S2 84
267 +#define CLK_I2S2_ASRC 85
268 +#define CLK_BUS_I2S0 86
269 +#define CLK_BUS_I2S1 87
270 +#define CLK_BUS_I2S2 88
271 +#define CLK_SPDIF_TX 89
272 +#define CLK_SPDIF_RX 90
273 +#define CLK_BUS_SPDIF 91
274 +#define CLK_DMIC 92
275 +#define CLK_BUS_DMIC 93
276 +#define CLK_AUDIO_DAC 94
277 +#define CLK_AUDIO_ADC 95
278 +#define CLK_BUS_AUDIO 96
279 +#define CLK_USB_OHCI0 97
280 +#define CLK_USB_OHCI1 98
281 +#define CLK_BUS_OHCI0 99
282 +#define CLK_BUS_OHCI1 100
283 +#define CLK_BUS_EHCI0 101
284 +#define CLK_BUS_EHCI1 102
285 +#define CLK_BUS_OTG 103
286 +#define CLK_BUS_LRADC 104
287 +#define CLK_BUS_DPSS_TOP 105
288 +#define CLK_HDMI_24M 106
289 +#define CLK_HDMI_CEC_32K 107
290 +#define CLK_HDMI_CEC 108
291 +#define CLK_BUS_HDMI 109
292 +#define CLK_MIPI_DSI 110
293 +#define CLK_BUS_MIPI_DSI 111
294 +#define CLK_TCON_LCD0 112
295 +#define CLK_BUS_TCON_LCD0 113
296 +#define CLK_TCON_TV 114
297 +#define CLK_BUS_TCON_TV 115
298 +#define CLK_TVE 116
299 +#define CLK_BUS_TVE_TOP 117
300 +#define CLK_BUS_TVE 118
301 +#define CLK_TVD 119
302 +#define CLK_BUS_TVD_TOP 120
303 +#define CLK_BUS_TVD 121
304 +#define CLK_LEDC 122
305 +#define CLK_BUS_LEDC 123
306 +#define CLK_CSI_TOP 124
307 +#define CLK_CSI_MCLK 125
308 +#define CLK_BUS_CSI 126
309 +#define CLK_TPADC 127
310 +#define CLK_BUS_TPADC 128
311 +#define CLK_BUS_TZMA 129
312 +#define CLK_DSP 130
313 +#define CLK_BUS_DSP_CFG 131
314 +#define CLK_RISCV 132
315 +#define CLK_RISCV_AXI 133
316 +#define CLK_BUS_RISCV_CFG 134
317 +#define CLK_FANOUT_24M 135
318 +#define CLK_FANOUT_12M 136
319 +#define CLK_FANOUT_16M 137
320 +#define CLK_FANOUT_25M 138
321 +#define CLK_FANOUT_32K 139
322 +#define CLK_FANOUT_27M 140
323 +#define CLK_FANOUT_PCLK 141
324 +#define CLK_FANOUT0 142
325 +#define CLK_FANOUT1 143
326 +#define CLK_FANOUT2 144
327 +#define CLK_BUS_CAN0 145
328 +#define CLK_BUS_CAN1 146
329 +
330 +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
331 diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h
332 new file mode 100644
333 index 0000000000..f8001cf50b
334 --- /dev/null
335 +++ b/include/dt-bindings/reset/sun20i-d1-ccu.h
336 @@ -0,0 +1,79 @@
337 +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
338 +/*
339 + * Copyright (c) 2020 huangzhenwei@allwinnertech.com
340 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
341 + */
342 +
343 +#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
344 +#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
345 +
346 +#define RST_MBUS 0
347 +#define RST_BUS_DE 1
348 +#define RST_BUS_DI 2
349 +#define RST_BUS_G2D 3
350 +#define RST_BUS_CE 4
351 +#define RST_BUS_VE 5
352 +#define RST_BUS_DMA 6
353 +#define RST_BUS_MSGBOX0 7
354 +#define RST_BUS_MSGBOX1 8
355 +#define RST_BUS_MSGBOX2 9
356 +#define RST_BUS_SPINLOCK 10
357 +#define RST_BUS_HSTIMER 11
358 +#define RST_BUS_DBG 12
359 +#define RST_BUS_PWM 13
360 +#define RST_BUS_DRAM 14
361 +#define RST_BUS_MMC0 15
362 +#define RST_BUS_MMC1 16
363 +#define RST_BUS_MMC2 17
364 +#define RST_BUS_UART0 18
365 +#define RST_BUS_UART1 19
366 +#define RST_BUS_UART2 20
367 +#define RST_BUS_UART3 21
368 +#define RST_BUS_UART4 22
369 +#define RST_BUS_UART5 23
370 +#define RST_BUS_I2C0 24
371 +#define RST_BUS_I2C1 25
372 +#define RST_BUS_I2C2 26
373 +#define RST_BUS_I2C3 27
374 +#define RST_BUS_SPI0 28
375 +#define RST_BUS_SPI1 29
376 +#define RST_BUS_EMAC 30
377 +#define RST_BUS_IR_TX 31
378 +#define RST_BUS_GPADC 32
379 +#define RST_BUS_THS 33
380 +#define RST_BUS_I2S0 34
381 +#define RST_BUS_I2S1 35
382 +#define RST_BUS_I2S2 36
383 +#define RST_BUS_SPDIF 37
384 +#define RST_BUS_DMIC 38
385 +#define RST_BUS_AUDIO 39
386 +#define RST_USB_PHY0 40
387 +#define RST_USB_PHY1 41
388 +#define RST_BUS_OHCI0 42
389 +#define RST_BUS_OHCI1 43
390 +#define RST_BUS_EHCI0 44
391 +#define RST_BUS_EHCI1 45
392 +#define RST_BUS_OTG 46
393 +#define RST_BUS_LRADC 47
394 +#define RST_BUS_DPSS_TOP 48
395 +#define RST_BUS_HDMI_SUB 49
396 +#define RST_BUS_HDMI_MAIN 50
397 +#define RST_BUS_MIPI_DSI 51
398 +#define RST_BUS_TCON_LCD0 52
399 +#define RST_BUS_TCON_TV 53
400 +#define RST_BUS_LVDS0 54
401 +#define RST_BUS_TVE 55
402 +#define RST_BUS_TVE_TOP 56
403 +#define RST_BUS_TVD 57
404 +#define RST_BUS_TVD_TOP 58
405 +#define RST_BUS_LEDC 59
406 +#define RST_BUS_CSI 60
407 +#define RST_BUS_TPADC 61
408 +#define RST_DSP 62
409 +#define RST_BUS_DSP_CFG 63
410 +#define RST_BUS_DSP_DBG 64
411 +#define RST_BUS_RISCV_CFG 65
412 +#define RST_BUS_CAN0 66
413 +#define RST_BUS_CAN1 67
414 +
415 +#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */
416 --
417 2.20.1
418
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