package/boot/uboot-sunxi/patches/4012-sunxi-clock-support-D1-R528-PLL6-clock.patch

   1 From 434dce1b0bfd9d3ab3a28352b596d27de3622796 Mon Sep 17 00:00:00 2001
   2 From: Andre Przywara <andre.przywara@arm.com>
   3 Date: Fri, 2 Dec 2022 21:48:19 +0000
   4 Subject: [PATCH 4012/4031] sunxi: clock: support D1/R528 PLL6 clock
   5
   6 The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is
   7 new P0 divider at bits [18:16], and the M divider is 1.
   8
   9 Add code to support this version of "PLL6".
  10
  11 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
  12 ---
  13  .../include/asm/arch-sunxi/clock_sun50i_h6.h  |  2 ++
  14  arch/arm/mach-sunxi/clock_sun50i_h6.c         | 24 +++++++++++++------
  15  2 files changed, 19 insertions(+), 7 deletions(-)
  16
  17 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
  18 index 9895c2c220..8471e11aa0 100644
  19 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
  20 +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
  21 @@ -249,6 +249,8 @@ struct sunxi_ccm_reg {
  22  #define CCM_PLL6_CTRL_EN               BIT(31)
  23  #define CCM_PLL6_LOCK_EN               BIT(29)
  24  #define CCM_PLL6_LOCK                  BIT(28)
  25 +#define CCM_PLL6_CTRL_P0_SHIFT         16
  26 +#define CCM_PLL6_CTRL_P0_MASK          (0x7 << CCM_PLL6_CTRL_P0_SHIFT)
  27  #define CCM_PLL6_CTRL_N_SHIFT          8
  28  #define CCM_PLL6_CTRL_N_MASK           (0xff << CCM_PLL6_CTRL_N_SHIFT)
  29  #define CCM_PLL6_CTRL_DIV1_SHIFT       0
  30 diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
  31 index 90110eab10..607efe6a9c 100644
  32 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
  33 +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
  34 @@ -107,16 +107,26 @@ unsigned int clock_get_pll6(void)
  35  {
  36         struct sunxi_ccm_reg *const ccm =
  37                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  38 -       int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2;
  39 -
  40         uint32_t rval = readl(&ccm->pll6_cfg);
  41         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
  42 -       int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
  43 -                       CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
  44         int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
  45 -                       CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
  46 -       /* The register defines PLL6-2X or PLL6-4X, not plain PLL6 */
  47 -       return 24000000 / m * n / div1 / div2;
  48 +                   CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
  49 +       int div1, m;
  50 +
  51 +       if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
  52 +               div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >>
  53 +                       CCM_PLL6_CTRL_P0_SHIFT) + 1;
  54 +               m = 1;
  55 +       } else {
  56 +               div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
  57 +                       CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
  58 +               if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
  59 +                       m = 4;
  60 +               else
  61 +                       m = 2;
  62 +       }
  63 +
  64 +       return 24000000U * n / m / div1 / div2;
  65  }
  66
  67  int clock_twi_onoff(int port, int state)
  68 --
  69 2.20.1
  70