package/boot/uboot-sunxi/patches/4006-pinctrl-sunxi-move-PIO_BASE-into-sunxi_gpio.h.patch

   1 From 69c0dbc968700d57189fd19e082f0f8a4b1df878 Mon Sep 17 00:00:00 2001
   2 From: Andre Przywara <andre.przywara@arm.com>
   3 Date: Tue, 6 Sep 2022 11:50:54 +0100
   4 Subject: [PATCH 4006/4031] pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h
   5
   6 On the Allwinner platform we were describing a quite comprehensive
   7 memory map in a per-SoC header unser arch/arm.
   8 In the old days that was used by every driver, but nowadays it should
   9 only be needed by SPL drivers (not using the DT). Many addresses in
  10 there were never used, and some are not needed anymore.
  11
  12 To avoid a dependency on CPU specific headers in an arch specific
  13 directory, move the definition of the pinctroller MMIO base address into
  14 the sunxi_gpio.h header, because the SPL routines for GPIO should be the
  15 only one needing this address.
  16 This is a first step towards getting rid of cpu_sun[x]i.h completely,
  17 and allows to remove the inclusion of that file from the sunxi_gpio.h
  18 header.
  19
  20 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
  21 ---
  22  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h     |  2 --
  23  arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h |  2 --
  24  arch/arm/include/asm/arch-sunxi/cpu_sun9i.h     |  2 --
  25  include/sunxi_gpio.h                            | 12 +++++++++++-
  26  4 files changed, 11 insertions(+), 7 deletions(-)
  27
  28 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
  29 index f7ecc790db..d6fe51f24b 100644
  30 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
  31 +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
  32 @@ -91,7 +91,6 @@
  33
  34  #define SUNXI_CCM_BASE                 0x01c20000
  35  #define SUNXI_INTC_BASE                        0x01c20400
  36 -#define SUNXI_PIO_BASE                 0x01c20800
  37  #define SUNXI_TIMER_BASE               0x01c20c00
  38  #ifndef CONFIG_SUNXI_GEN_SUN6I
  39  #define SUNXI_PWM_BASE                 0x01c20e00
  40 @@ -210,7 +209,6 @@ defined(CONFIG_MACH_SUN50I)
  41
  42  #define SUNXI_R_TWI_BASE               0x01f02400
  43  #define SUNXI_R_UART_BASE              0x01f02800
  44 -#define SUNXI_R_PIO_BASE               0x01f02c00
  45  #define SUN6I_P2WI_BASE                        0x01f03400
  46  #define SUNXI_RSB_BASE                 0x01f03400
  47
  48 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
  49 index d9cf8ae042..9b6bf84360 100644
  50 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
  51 +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
  52 @@ -22,7 +22,6 @@
  53  #define SUNXI_SIDC_BASE                        0x03006000
  54  #define SUNXI_SID_BASE                 0x03006200
  55  #define SUNXI_TIMER_BASE               0x03009000
  56 -#define SUNXI_PIO_BASE                 0x0300B000
  57  #define SUNXI_PSI_BASE                 0x0300C000
  58
  59  #define SUNXI_GIC400_BASE              0x03020000
  60 @@ -68,7 +67,6 @@
  61  #define SUNXI_R_CPUCFG_BASE            0x07000400
  62  #define SUNXI_PRCM_BASE                        0x07010000
  63  #define SUNXI_R_WDOG_BASE              0x07020400
  64 -#define SUNXI_R_PIO_BASE               0x07022000
  65  #define SUNXI_R_UART_BASE              0x07080000
  66  #define SUNXI_R_TWI_BASE               0x07081400
  67
  68 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
  69 index 9c2d11b590..20025be231 100644
  70 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
  71 +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
  72 @@ -81,7 +81,6 @@
  73  /* APB0 Module */
  74  #define SUNXI_CCM_BASE                 (REGS_APB0_BASE + 0x0000)
  75  #define SUNXI_CCMMODULE_BASE           (REGS_APB0_BASE + 0x0400)
  76 -#define SUNXI_PIO_BASE                 (REGS_APB0_BASE + 0x0800)
  77  #define SUNXI_TIMER_BASE               (REGS_APB0_BASE + 0x0C00)
  78  #define SUNXI_PWM_BASE                 (REGS_APB0_BASE + 0x1400)
  79  #define SUNXI_LRADC_BASE               (REGS_APB0_BASE + 0x1800)
  80 @@ -102,7 +101,6 @@
  81  /* RCPUS Module */
  82  #define SUNXI_PRCM_BASE                        (REGS_RCPUS_BASE + 0x1400)
  83  #define SUNXI_R_UART_BASE              (REGS_RCPUS_BASE + 0x2800)
  84 -#define SUNXI_R_PIO_BASE               (REGS_RCPUS_BASE + 0x2c00)
  85  #define SUNXI_RSB_BASE                 (REGS_RCPUS_BASE + 0x3400)
  86
  87  /* Misc. */
  88 diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
  89 index 42ca03d8c1..5ac476f960 100644
  90 --- a/include/sunxi_gpio.h
  91 +++ b/include/sunxi_gpio.h
  92 @@ -9,7 +9,17 @@
  93  #define _SUNXI_GPIO_H
  94
  95  #include <linux/types.h>
  96 -#include <asm/arch/cpu.h>
  97 +
  98 +#if defined(CONFIG_MACH_SUN9I)
  99 +#define SUNXI_PIO_BASE         0x06000800
 100 +#define SUNXI_R_PIO_BASE       0x08002c00
 101 +#elif defined(CONFIG_SUN50I_GEN_H6)
 102 +#define SUNXI_PIO_BASE         0x0300b000
 103 +#define SUNXI_R_PIO_BASE       0x07022000
 104 +#else
 105 +#define SUNXI_PIO_BASE         0x01c20800
 106 +#define SUNXI_R_PIO_BASE       0x01f02c00
 107 +#endif
 108
 109  /*
 110   * sunxi has 9 banks of gpio, they are:
 111 --
 112 2.20.1
 113