include/arch/aarch64/el3_common_macros.S

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef EL3_COMMON_MACROS_S
   8 #define EL3_COMMON_MACROS_S
   9
  10 #include <arch.h>
  11 #include <asm_macros.S>
  12
  13         /*
  14          * Helper macro to initialise EL3 registers we care about.
  15          */
  16         .macro el3_arch_init_common
  17         /* ---------------------------------------------------------------------
  18          * SCTLR_EL3 has already been initialised - read current value before
  19          * modifying.
  20          *
  21          * SCTLR_EL3.I: Enable the instruction cache.
  22          *
  23          * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault
  24          *  exception is generated if a load or store instruction executed at
  25          *  EL3 uses the SP as the base address and the SP is not aligned to a
  26          *  16-byte boundary.
  27          *
  28          * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that
  29          *  load or store one or more registers have an alignment check that the
  30          *  address being accessed is aligned to the size of the data element(s)
  31          *  being accessed.
  32          * ---------------------------------------------------------------------
  33          */
  34         mov     x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
  35         mrs     x0, sctlr_el3
  36         orr     x0, x0, x1
  37         msr     sctlr_el3, x0
  38         isb
  39
  40 #ifdef IMAGE_BL31
  41         /* ---------------------------------------------------------------------
  42          * Initialise the per-cpu cache pointer to the CPU.
  43          * This is done early to enable crash reporting to have access to crash
  44          * stack. Since crash reporting depends on cpu_data to report the
  45          * unhandled exception, not doing so can lead to recursive exceptions
  46          * due to a NULL TPIDR_EL3.
  47          * ---------------------------------------------------------------------
  48          */
  49         bl      init_cpu_data_ptr
  50 #endif /* IMAGE_BL31 */
  51
  52         /* ---------------------------------------------------------------------
  53          * Initialise SCR_EL3, setting all fields rather than relying on hw.
  54          * All fields are architecturally UNKNOWN on reset. The following fields
  55          * do not change during the TF lifetime. The remaining fields are set to
  56          * zero here but are updated ahead of transitioning to a lower EL in the
  57          * function cm_init_context_common().
  58          *
  59          * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
  60          *  EL2, EL1 and EL0 are not trapped to EL3.
  61          *
  62          * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
  63          *  EL2, EL1 and EL0 are not trapped to EL3.
  64          *
  65          * SCR_EL3.SIF: Set to one to disable instruction fetches from
  66          *  Non-secure memory.
  67          *
  68          * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
  69          *  both Security states and both Execution states.
  70          *
  71          * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
  72          *  to EL3 when executing at any EL.
  73          *
  74          * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature,
  75          * disable traps to EL3 when accessing key registers or using pointer
  76          * authentication instructions from lower ELs.
  77          * ---------------------------------------------------------------------
  78          */
  79         mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT | \
  80                                 SCR_API_BIT | SCR_APK_BIT) \
  81                         & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT))
  82         msr     scr_el3, x0
  83
  84         /* ---------------------------------------------------------------------
  85          * Initialise MDCR_EL3, setting all fields rather than relying on hw.
  86          * Some fields are architecturally UNKNOWN on reset.
  87          *
  88          * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
  89          *  Debug exceptions, other than Breakpoint Instruction exceptions, are
  90          *  disabled from all ELs in Secure state.
  91          *
  92          * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
  93          *  privileged debug from S-EL1.
  94          *
  95          * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
  96          *  access to the powerdown debug registers do not trap to EL3.
  97          *
  98          * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
  99          *  debug registers, other than those registers that are controlled by
 100          *  MDCR_EL3.TDOSA.
 101          *
 102          * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
 103          *  accesses to all Performance Monitors registers do not trap to EL3.
 104          * ---------------------------------------------------------------------
 105          */
 106         mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) \
 107                         & ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT))
 108         msr     mdcr_el3, x0
 109
 110         /* ---------------------------------------------------------------------
 111          * Enable External Aborts and SError Interrupts now that the exception
 112          * vectors have been setup.
 113          * ---------------------------------------------------------------------
 114          */
 115         msr     daifclr, #DAIF_ABT_BIT
 116
 117         /* ---------------------------------------------------------------------
 118          * Initialise CPTR_EL3, setting all fields rather than relying on hw.
 119          * All fields are architecturally UNKNOWN on reset.
 120          *
 121          * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1,
 122          *  CPTR_EL2, CPACR, or HCPTR do not trap to EL3.
 123          *
 124          * CPTR_EL3.TTA: Set to zero so that System register accesses to the
 125          *  trace registers do not trap to EL3.
 126          *
 127          * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
 128          *  by Advanced SIMD, floating-point or SVE instructions (if implemented)
 129          *  do not trap to EL3.
 130          */
 131         mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT))
 132         msr     cptr_el3, x0
 133
 134         /*
 135          * If Data Independent Timing (DIT) functionality is implemented,
 136          * always enable DIT in EL3
 137          */
 138         mrs     x0, id_aa64pfr0_el1
 139         ubfx    x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
 140         cmp     x0, #ID_AA64PFR0_DIT_SUPPORTED
 141         bne     1f
 142         mov     x0, #DIT_BIT
 143         msr     DIT, x0
 144 1:
 145         .endm
 146
 147 /* -----------------------------------------------------------------------------
 148  * This is the super set of actions that need to be performed during a cold boot
 149  * or a warm boot in EL3. This code is shared by BL1 and BL31.
 150  *
 151  * This macro will always perform reset handling, architectural initialisations
 152  * and stack setup. The rest of the actions are optional because they might not
 153  * be needed, depending on the context in which this macro is called. This is
 154  * why this macro is parameterised ; each parameter allows to enable/disable
 155  * some actions.
 156  *
 157  *  _init_sctlr:
 158  *      Whether the macro needs to initialise SCTLR_EL3, including configuring
 159  *      the endianness of data accesses.
 160  *
 161  *  _warm_boot_mailbox:
 162  *      Whether the macro needs to detect the type of boot (cold/warm). The
 163  *      detection is based on the platform entrypoint address : if it is zero
 164  *      then it is a cold boot, otherwise it is a warm boot. In the latter case,
 165  *      this macro jumps on the platform entrypoint address.
 166  *
 167  *  _secondary_cold_boot:
 168  *      Whether the macro needs to identify the CPU that is calling it: primary
 169  *      CPU or secondary CPU. The primary CPU will be allowed to carry on with
 170  *      the platform initialisations, while the secondaries will be put in a
 171  *      platform-specific state in the meantime.
 172  *
 173  *      If the caller knows this macro will only be called by the primary CPU
 174  *      then this parameter can be defined to 0 to skip this step.
 175  *
 176  * _init_memory:
 177  *      Whether the macro needs to initialise the memory.
 178  *
 179  * _init_c_runtime:
 180  *      Whether the macro needs to initialise the C runtime environment.
 181  *
 182  * _exception_vectors:
 183  *      Address of the exception vectors to program in the VBAR_EL3 register.
 184  * -----------------------------------------------------------------------------
 185  */
 186         .macro el3_entrypoint_common                                    \
 187                 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot,  \
 188                 _init_memory, _init_c_runtime, _exception_vectors
 189
 190         .if \_init_sctlr
 191                 /* -------------------------------------------------------------
 192                  * This is the initialisation of SCTLR_EL3 and so must ensure
 193                  * that all fields are explicitly set rather than relying on hw.
 194                  * Some fields reset to an IMPLEMENTATION DEFINED value and
 195                  * others are architecturally UNKNOWN on reset.
 196                  *
 197                  * SCTLR.EE: Set the CPU endianness before doing anything that
 198                  *  might involve memory reads or writes. Set to zero to select
 199                  *  Little Endian.
 200                  *
 201                  * SCTLR_EL3.WXN: For the EL3 translation regime, this field can
 202                  *  force all memory regions that are writeable to be treated as
 203                  *  XN (Execute-never). Set to zero so that this control has no
 204                  *  effect on memory access permissions.
 205                  *
 206                  * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
 207                  *
 208                  * SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
 209                  *
 210                  * SCTLR.DSSBS: Set to zero to disable speculation store bypass
 211                  *  safe behaviour upon exception entry to EL3.
 212                  * -------------------------------------------------------------
 213                  */
 214                 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
 215                                 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT))
 216                 msr     sctlr_el3, x0
 217                 isb
 218         .endif /* _init_sctlr */
 219
 220         .if \_warm_boot_mailbox
 221                 /* -------------------------------------------------------------
 222                  * This code will be executed for both warm and cold resets.
 223                  * Now is the time to distinguish between the two.
 224                  * Query the platform entrypoint address and if it is not zero
 225                  * then it means it is a warm boot so jump to this address.
 226                  * -------------------------------------------------------------
 227                  */
 228                 bl      plat_get_my_entrypoint
 229                 cbz     x0, do_cold_boot
 230                 br      x0
 231
 232         do_cold_boot:
 233         .endif /* _warm_boot_mailbox */
 234
 235         /* ---------------------------------------------------------------------
 236          * Set the exception vectors.
 237          * ---------------------------------------------------------------------
 238          */
 239         adr     x0, \_exception_vectors
 240         msr     vbar_el3, x0
 241         isb
 242
 243         /* ---------------------------------------------------------------------
 244          * It is a cold boot.
 245          * Perform any processor specific actions upon reset e.g. cache, TLB
 246          * invalidations etc.
 247          * ---------------------------------------------------------------------
 248          */
 249         bl      reset_handler
 250
 251         el3_arch_init_common
 252
 253         .if \_secondary_cold_boot
 254                 /* -------------------------------------------------------------
 255                  * Check if this is a primary or secondary CPU cold boot.
 256                  * The primary CPU will set up the platform while the
 257                  * secondaries are placed in a platform-specific state until the
 258                  * primary CPU performs the necessary actions to bring them out
 259                  * of that state and allows entry into the OS.
 260                  * -------------------------------------------------------------
 261                  */
 262                 bl      plat_is_my_cpu_primary
 263                 cbnz    w0, do_primary_cold_boot
 264
 265                 /* This is a cold boot on a secondary CPU */
 266                 bl      plat_secondary_cold_boot_setup
 267                 /* plat_secondary_cold_boot_setup() is not supposed to return */
 268                 bl      el3_panic
 269
 270         do_primary_cold_boot:
 271         .endif /* _secondary_cold_boot */
 272
 273         /* ---------------------------------------------------------------------
 274          * Initialize memory now. Secondary CPU initialization won't get to this
 275          * point.
 276          * ---------------------------------------------------------------------
 277          */
 278
 279         .if \_init_memory
 280                 bl      platform_mem_init
 281         .endif /* _init_memory */
 282
 283         /* ---------------------------------------------------------------------
 284          * Init C runtime environment:
 285          *   - Zero-initialise the NOBITS sections. There are 2 of them:
 286          *       - the .bss section;
 287          *       - the coherent memory section (if any).
 288          *   - Relocate the data section from ROM to RAM, if required.
 289          * ---------------------------------------------------------------------
 290          */
 291         .if \_init_c_runtime
 292 #if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
 293                 /* -------------------------------------------------------------
 294                  * Invalidate the RW memory used by the BL31 image. This
 295                  * includes the data and NOBITS sections. This is done to
 296                  * safeguard against possible corruption of this memory by
 297                  * dirty cache lines in a system cache as a result of use by
 298                  * an earlier boot loader stage.
 299                  * -------------------------------------------------------------
 300                  */
 301                 adrp    x0, __RW_START__
 302                 add     x0, x0, :lo12:__RW_START__
 303                 adrp    x1, __RW_END__
 304                 add     x1, x1, :lo12:__RW_END__
 305                 sub     x1, x1, x0
 306                 bl      inv_dcache_range
 307 #endif
 308                 adrp    x0, __BSS_START__
 309                 add     x0, x0, :lo12:__BSS_START__
 310
 311                 adrp    x1, __BSS_END__
 312                 add     x1, x1, :lo12:__BSS_END__
 313                 sub     x1, x1, x0
 314                 bl      zeromem
 315
 316 #if USE_COHERENT_MEM
 317                 adrp    x0, __COHERENT_RAM_START__
 318                 add     x0, x0, :lo12:__COHERENT_RAM_START__
 319                 adrp    x1, __COHERENT_RAM_END_UNALIGNED__
 320                 add     x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__
 321                 sub     x1, x1, x0
 322                 bl      zeromem
 323 #endif
 324
 325 #if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM)
 326                 adrp    x0, __DATA_RAM_START__
 327                 add     x0, x0, :lo12:__DATA_RAM_START__
 328                 adrp    x1, __DATA_ROM_START__
 329                 add     x1, x1, :lo12:__DATA_ROM_START__
 330                 adrp    x2, __DATA_RAM_END__
 331                 add     x2, x2, :lo12:__DATA_RAM_END__
 332                 sub     x2, x2, x0
 333                 bl      memcpy16
 334 #endif
 335         .endif /* _init_c_runtime */
 336
 337         /* ---------------------------------------------------------------------
 338          * Use SP_EL0 for the C runtime stack.
 339          * ---------------------------------------------------------------------
 340          */
 341         msr     spsel, #0
 342
 343         /* ---------------------------------------------------------------------
 344          * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
 345          * the MMU is enabled. There is no risk of reading stale stack memory
 346          * after enabling the MMU as only the primary CPU is running at the
 347          * moment.
 348          * ---------------------------------------------------------------------
 349          */
 350         bl      plat_set_my_stack
 351
 352 #if STACK_PROTECTOR_ENABLED
 353         .if \_init_c_runtime
 354         bl      update_stack_protector_canary
 355         .endif /* _init_c_runtime */
 356 #endif
 357         .endm
 358
 359 #endif /* EL3_COMMON_MACROS_S */