1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 Linaro
4 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <dm/platform_data/serial_pl01x.h>
11 #include <asm/arch/hi3798cv200.h>
12 #include <asm/arch/dwmmc.h>
13 #include <asm/armv8/mmu.h>
15 DECLARE_GLOBAL_DATA_PTR
;
17 static struct mm_region poplar_mem_map
[] = {
22 .attrs
= PTE_BLOCK_MEMTYPE(MT_NORMAL
) |
28 .attrs
= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE
) |
30 PTE_BLOCK_PXN
| PTE_BLOCK_UXN
36 struct mm_region
*mem_map
= poplar_mem_map
;
38 #if !CONFIG_IS_ENABLED(OF_CONTROL)
39 static const struct pl01x_serial_platdata serial_platdata
= {
40 .base
= REG_BASE_UART0
,
45 U_BOOT_DEVICE(poplar_serial
) = {
46 .name
= "serial_pl01x",
47 .platdata
= &serial_platdata
,
53 puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
58 void reset_cpu(ulong addr
)
65 gd
->ram_size
= get_ram_size(NULL
, 0x80000000);
71 * Some linux kernel versions don't use memory before its load address, so to
72 * be generic we just pretend it isn't there. In previous uboot versions we
73 * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
74 * could persist in memory and be left alone by the kernel.
76 * That led to a problem when mapping memory in older kernels. That PSCI code
77 * now lies in memory below the kernel load offset; it therefore won't be
78 * touched by the kernel, and by not specially reserving it we avoid the mapping
82 #define KERNEL_TEXT_OFFSET 0x00080000
84 int dram_init_banksize(void)
86 gd
->bd
->bi_dram
[0].start
= KERNEL_TEXT_OFFSET
;
87 gd
->bd
->bi_dram
[0].size
= gd
->ram_size
- gd
->bd
->bi_dram
[0].start
;
92 static void usb2_phy_config(void)
94 const u32 config
[] = {
95 /* close EOP pre-emphasis. open data pre-emphasis */
97 /* Rcomp = 150mW, increase DC level */
99 /* keep Rcomp working */
101 /* Icomp = 212mW, increase current drive */
103 /* EMI fix: rx_active not stay 1 when error packets received */
105 /* Comp mode select */
107 /* adjust eye diagram */
109 /* adjust eye diagram */
114 for (i
= 0; i
< ARRAY_SIZE(config
); i
++) {
115 writel(config
[i
], PERI_CTRL_USB0
);
116 clrsetbits_le32(PERI_CTRL_USB0
, BIT(21), BIT(20) | BIT(22));
121 static void usb2_phy_init(void)
123 /* reset usb2 controller bus/utmi/roothub */
124 setbits_le32(PERI_CRG46
, USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ
|
125 USB2_HST_PHY_SYST_REQ
| USB2_OTG_PHY_SYST_REQ
);
128 /* reset usb2 phy por/utmi */
129 setbits_le32(PERI_CRG47
, USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1
);
132 /* open usb2 ref clk */
133 setbits_le32(PERI_CRG47
, USB2_PHY01_REF_CKEN
);
136 /* cancel usb2 power on reset */
137 clrbits_le32(PERI_CRG47
, USB2_PHY01_SRST_REQ
);
142 /* cancel usb2 port reset, wait comp circuit stable */
143 clrbits_le32(PERI_CRG47
, USB2_PHY01_SRST_TREQ1
);
146 /* open usb2 controller clk */
147 setbits_le32(PERI_CRG46
, USB2_BUS_CKEN
| USB2_OHCI48M_CKEN
|
148 USB2_OHCI12M_CKEN
| USB2_OTG_UTMI_CKEN
|
149 USB2_HST_PHY_CKEN
| USB2_UTMI0_CKEN
);
152 /* cancel usb2 control reset */
153 clrbits_le32(PERI_CRG46
, USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ
|
154 USB2_HST_PHY_SYST_REQ
| USB2_OTG_PHY_SYST_REQ
);
158 int board_mmc_init(bd_t
*bis
)
162 ret
= hi6220_dwmci_add_port(0, REG_BASE_MCI
, 8);
164 printf("mmc init error (%d)\n", ret
);
169 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
171 #include <usb/dwc2_udc.h>
174 static struct dwc2_plat_otg_data poplar_otg_data
= {
175 .regs_otg
= HIOTG_BASE_ADDR
178 static void set_usb_to_device(void)
180 setbits_le32(PERI_CTRL_USB3
, USB2_2P_CHIPID
);
183 int board_usb_init(int index
, enum usb_init_type init
)
186 return dwc2_udc_probe(&poplar_otg_data
);
189 int g_dnl_bind_fixup(struct usb_device_descriptor
*dev
, const char *name
)
191 if (!env_get("serial#"))
192 g_dnl_set_serialnumber("0123456789POPLAR");