MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODE

Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT
(or CONF_CM_CACHABLE_COW when a CM is available). There is no
need to make this configurable.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/README b/README
index 21d1f8a007ba8c33360017f79f6524897abd6c6e..f7ed7eaae16c8460625a6b38727dfab3db7fdb9e 100644 (file)
--- a/README
+++ b/README
@@ -528,20 +528,6 @@ The following options need to be configured:
                pointer. This is needed for the temporary stack before
                relocation.
 
-               CONFIG_SYS_MIPS_CACHE_MODE
-
-               Cache operation mode for the MIPS CPU.
-               See also arch/mips/include/asm/mipsregs.h.
-               Possible values are:
-                       CONF_CM_CACHABLE_NO_WA
-                       CONF_CM_CACHABLE_WA
-                       CONF_CM_UNCACHED
-                       CONF_CM_CACHABLE_NONCOHERENT
-                       CONF_CM_CACHABLE_CE
-                       CONF_CM_CACHABLE_COW
-                       CONF_CM_CACHABLE_CUW
-                       CONF_CM_CACHABLE_ACCELERATED
-
                CONFIG_XWAY_SWAP_BYTES
 
                Enable compilation of tools/xway-swap-bytes needed for Lantiq

diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 5616ee6dfd6efb5d3b70ba103a72a411e63c510a..cfad1d9c8a97050b001846efdd971601089b3663 100644 (file)
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -14,10 +14,6 @@
 #include <asm/cacheops.h>
 #include <asm/cm.h>
 
-#ifndef CONFIG_SYS_MIPS_CACHE_MODE
-#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
-#endif
-
        .macro  f_fill64 dst, offset, val
        LONG_S  \val, (\offset +  0 * LONGSIZE)(\dst)
        LONG_S  \val, (\offset +  1 * LONGSIZE)(\dst)
@@ -331,7 +327,7 @@ l1_init:
        and             t0, t0, t1
        PTR_LI          t1, CKSEG1
        or              t0, t0, t1
-       li              a0, CONFIG_SYS_MIPS_CACHE_MODE
+       li              a0, CONF_CM_CACHABLE_NONCOHERENT
        jalr.hb         t0
 
        /*

diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h
index 29b23fa40e501623b7d0f66519375c4889090afb..8e2d72323d62121c3ed38683b85164c4b16b7e4a 100644 (file)
--- a/include/configs/imgtec_xilfpga.h
+++ b/include/configs/imgtec_xilfpga.h
@@ -19,9 +19,6 @@
 /* CPU Timer rate */
 #define CONFIG_SYS_MIPS_TIMER_FREQ     50000000
 
-/* Cache Configuration */
-#define CONFIG_SYS_MIPS_CACHE_MODE     CONF_CM_CACHABLE_NONCOHERENT
-
 /*----------------------------------------------------------------------
  * Memory Layout
  */

diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 374957737ddf5cb04188b781be3ee9f4ba8df2e0..d3ab5575ee704702487dcffca9613b0f6c00d9d5 100644 (file)
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -16,9 +16,6 @@
 /* CPU Timer rate */
 #define CONFIG_SYS_MIPS_TIMER_FREQ     100000000
 
-/* Cache Configuration */
-#define CONFIG_SYS_MIPS_CACHE_MODE     CONF_CM_CACHABLE_NONCOHERENT
-
 /*----------------------------------------------------------------------
  * Memory Layout
  */

diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 15c1cc08b79c1b0e8250ec1bd66eb151641c2def..e058a06e8f9a9070928f7e4a7e927a8f506b737d 100644 (file)
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3424,7 +3424,6 @@ CONFIG_SYS_MEM_TOP_HIDE
 CONFIG_SYS_MFD
 CONFIG_SYS_MHZ
 CONFIG_SYS_MII_MODE
-CONFIG_SYS_MIPS_CACHE_MODE
 CONFIG_SYS_MIPS_TIMER_FREQ
 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR