ipq40xx: convert to nvmem-layout
[openwrt/staging/hauke.git] / target / linux / ipq40xx / files / arch / arm / boot / dts / qcom-ipq4018-ecw5211.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/soc/qcom,tcsr.h>
7
8 / {
9 model = "Edgecore ECW5211";
10 compatible = "edgecore,ecw5211";
11
12 aliases {
13 led-boot = &led_power;
14 led-failsafe = &led_power;
15 led-running = &led_power;
16 led-upgrade = &led_power;
17 ethernet0 = &swport5;
18 ethernet1 = &gmac;
19 };
20
21 chosen {
22 bootargs-append = " root=/dev/ubiblock0_1";
23 };
24
25 keys {
26 compatible = "gpio-keys";
27
28 reset {
29 label = "reset";
30 gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
31 linux,code = <KEY_RESTART>;
32 };
33 };
34
35 leds {
36 compatible = "gpio-leds";
37
38 led_power: power {
39 label = "yellow:power";
40 gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
41 };
42
43 wlan2g {
44 label = "green:wlan2g";
45 gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
46 linux,default-trigger = "phy0tpt";
47 };
48
49 wlan5g {
50 label = "green:wlan5g";
51 gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
52 linux,default-trigger = "phy1tpt";
53 };
54 };
55
56 soc {
57 rng@22000 {
58 status = "okay";
59 };
60
61 counter@4a1000 {
62 compatible = "qcom,qca-gcnt";
63 reg = <0x4a1000 0x4>;
64 };
65
66 tcsr@1949000 {
67 compatible = "qcom,tcsr";
68 reg = <0x1949000 0x100>;
69 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
70 };
71
72 tcsr@194b000 {
73 compatible = "qcom,tcsr";
74 reg = <0x194b000 0x100>;
75 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
76 };
77
78 ess_tcsr@1953000 {
79 compatible = "qcom,tcsr";
80 reg = <0x1953000 0x1000>;
81 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
82 };
83
84 tcsr@1957000 {
85 compatible = "qcom,tcsr";
86 reg = <0x1957000 0x100>;
87 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
88 };
89
90 usb2@60f8800 {
91 status = "okay";
92 };
93
94 usb3@8af8800 {
95 status = "okay";
96
97 dwc3@8a00000 {
98 phys = <&usb3_hs_phy>;
99 phy-names = "usb2-phy";
100 };
101 };
102
103 crypto@8e3a000 {
104 status = "okay";
105 };
106
107 watchdog@b017000 {
108 status = "okay";
109 };
110 };
111 };
112
113 &tlmm {
114 mdio_pins: mdio_pinmux {
115 mux_mdio {
116 pins = "gpio53";
117 function = "mdio";
118 bias-pull-up;
119 };
120
121 mux_mdc {
122 pins = "gpio52";
123 function = "mdc";
124 bias-pull-up;
125 };
126 };
127
128 serial_pins: serial_pinmux {
129 mux {
130 pins = "gpio60", "gpio61";
131 function = "blsp_uart0";
132 bias-disable;
133 };
134 };
135
136 spi0_pins: spi0_pinmux {
137 pin {
138 function = "blsp_spi0";
139 pins = "gpio55", "gpio56", "gpio57";
140 drive-strength = <2>;
141 bias-disable;
142 };
143
144 pin_cs {
145 function = "gpio";
146 pins = "gpio54", "gpio4";
147 drive-strength = <2>;
148 bias-disable;
149 output-high;
150 };
151 };
152
153 i2c0_pins: i2c0_pinmux {
154 mux_i2c {
155 function = "blsp_i2c0";
156 pins = "gpio58", "gpio59";
157 drive-strength = <16>;
158 bias-disable;
159 };
160 };
161 };
162
163 &blsp_dma {
164 status = "okay";
165 };
166
167 &blsp1_spi1 {
168 status = "okay";
169
170 pinctrl-0 = <&spi0_pins>;
171 pinctrl-names = "default";
172 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
173
174 flash@0 {
175 compatible = "jedec,spi-nor";
176 reg = <0>;
177 spi-max-frequency = <24000000>;
178
179 partitions {
180 compatible = "fixed-partitions";
181 #address-cells = <1>;
182 #size-cells = <1>;
183
184 partition@0 {
185 label = "0:SBL1";
186 reg = <0x00000000 0x00040000>;
187 read-only;
188 };
189
190 partition@40000 {
191 label = "0:MIBIB";
192 reg = <0x00040000 0x00020000>;
193 read-only;
194 };
195
196 partition@60000 {
197 label = "0:QSEE";
198 reg = <0x00060000 0x00060000>;
199 read-only;
200 };
201
202 partition@c0000 {
203 label = "0:CDT";
204 reg = <0x000c0000 0x00010000>;
205 read-only;
206 };
207
208 partition@d0000 {
209 label = "0:DDRPARAMS";
210 reg = <0x000d0000 0x00010000>;
211 read-only;
212 };
213
214 partition@e0000 {
215 label = "0:APPSBLENV"; /* uboot env */
216 reg = <0x000e0000 0x00010000>;
217 };
218
219 partition@f0000 {
220 label = "0:APPSBL"; /* uboot */
221 reg = <0x000f0000 0x00080000>;
222 read-only;
223 };
224
225 partition@170000 {
226 label = "0:ART";
227 reg = <0x00170000 0x00010000>;
228 read-only;
229
230 nvmem-layout {
231 compatible = "fixed-layout";
232 #address-cells = <1>;
233 #size-cells = <1>;
234
235 precal_art_1000: precal@1000 {
236 reg = <0x1000 0x2f20>;
237 };
238
239 precal_art_5000: precal@5000 {
240 reg = <0x5000 0x2f20>;
241 };
242 };
243 };
244 };
245 };
246
247 flash@1 {
248 compatible = "spi-nand";
249 reg = <1>;
250 spi-max-frequency = <24000000>;
251
252 partitions {
253 compatible = "fixed-partitions";
254 #address-cells = <1>;
255 #size-cells = <1>;
256
257 partition@0 {
258 label = "rootfs";
259 reg = <0x00000000 0x04000000>;
260 };
261 };
262 };
263 };
264
265 &blsp1_i2c3 {
266 status = "okay";
267
268 pinctrl-0 = <&i2c0_pins>;
269 pinctrl-names = "default";
270
271 tpm@29 {
272 compatible = "atmel,at97sc3204t";
273 reg = <0x29>;
274 };
275 };
276
277 &blsp1_uart1 {
278 status = "okay";
279
280 pinctrl-0 = <&serial_pins>;
281 pinctrl-names = "default";
282 };
283
284 &cryptobam {
285 status = "okay";
286 };
287
288 &mdio {
289 status = "okay";
290
291 pinctrl-0 = <&mdio_pins>;
292 pinctrl-names = "default";
293 };
294
295 &gmac {
296 status = "okay";
297 };
298
299 &switch {
300 status = "okay";
301 };
302
303 &swport4 {
304 status = "okay";
305
306 label = "lan";
307 };
308
309 &swport5 {
310 status = "okay";
311 };
312
313 &wifi0 {
314 status = "okay";
315 nvmem-cell-names = "pre-calibration";
316 nvmem-cells = <&precal_art_1000>;
317 };
318
319 &wifi1 {
320 status = "okay";
321 nvmem-cell-names = "pre-calibration";
322 nvmem-cells = <&precal_art_5000>;
323 qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
324 };
325
326 &usb3_hs_phy {
327 status = "okay";
328 };
329
330 &usb2_hs_phy {
331 status = "okay";
332 };