plat/bcm/include/pmc_addr_63158.h

   1 /*
   2 <:copyright-BRCM:2019:DUAL/GPL:standard
   3
   4    Copyright (c) 2019 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22 */
  23
  24 #ifndef PMC_ADDR_63158_H__
  25 #define PMC_ADDR_63158_H__
  26
  27 #define PMB_BUS_MAX              2
  28 #define PMB_BUS_ID_SHIFT         8
  29
  30 #define PMB_BUS_PERIPH           1
  31 #define PMB_ADDR_PERIPH          (3 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
  32 #define PMB_ZONES_PERIPH         4
  33
  34 #define PMB_BUS_CHIP_CLKRST      0
  35 #define PMB_ADDR_CHIP_CLKRST     (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
  36 #define PMB_ZONES_CHIP_CLKRST    0
  37
  38 #define BPCM_CLKRST_AFE_PWRDWN   0x80000000
  39
  40 #define PMB_BUS_SYSPLL           0
  41 #define PMB_ADDR_SYSPLL          (4 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
  42 #define PMB_ZONES_SYSPLL         0
  43
  44 #define PMB_BUS_RDPPLL           0
  45 #define PMB_ADDR_RDPPLL          (6 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
  46 #define PMB_ZONES_RDPPLL         0
  47
  48 #define PMB_BUS_UBUSPLL          0
  49 #define PMB_ADDR_UBUSPLL         (5 | PMB_BUS_UBUSPLL << PMB_BUS_ID_SHIFT)
  50 #define PMB_ZONES_UBUSPLL        0
  51
  52 #define PMB_BUS_MEMC             0
  53 #define PMB_ADDR_MEMC            (2 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
  54 #define PMB_ZONES_MEMC           1
  55
  56 #define PMB_BUS_SYNC_PLL         1
  57 #define PMB_ADDR_SYNC_PLL        (7 | PMB_BUS_SYNC_PLL << PMB_BUS_ID_SHIFT)
  58 #define PMB_ZONES_SYNC_PLL       1
  59
  60 #define PMB_BUS_USB30_2X         1
  61 #define PMB_ADDR_USB30_2X        (13 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
  62 #define PMB_ZONES_USB30_2X       4
  63
  64 #define PMB_BUS_WAN              1
  65 #define PMB_ADDR_WAN             (15 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT)
  66 #define PMB_ZONES_WAN            7
  67
  68 #define PMB_BUS_XRDP             1
  69 #define PMB_ADDR_XRDP            (16 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
  70 #define PMB_ZONES_XRDP           3
  71
  72 #define PMB_BUS_PCIE0            0
  73 #define PMB_ADDR_PCIE0           (8 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
  74 #define PMB_ZONES_PCIE0          1
  75
  76 #define PMB_BUS_PCIE1            0
  77 #define PMB_ADDR_PCIE1           (9 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
  78 #define PMB_ZONES_PCIE1          1
  79
  80 #define PMB_BUS_PCIE2            0
  81 #define PMB_ADDR_PCIE2           (10 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT)
  82 #define PMB_ZONES_PCIE2          1
  83
  84 #define PMB_BUS_PCIE3            1
  85 #define PMB_ADDR_PCIE3           (12 | PMB_BUS_PCIE3 << PMB_BUS_ID_SHIFT)
  86 #define PMB_ZONES_PCIE3          1
  87
  88 #define PMB_BUS_SATA             0
  89 #define PMB_ADDR_SATA            (11 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
  90 #define PMB_ZONES_SATA           1
  91
  92 #define PMB_BUS_SGMII            1
  93 #define PMB_ADDR_SGMII           (14 | PMB_BUS_SGMII << PMB_BUS_ID_SHIFT)
  94 #define PMB_ZONES_SGMII          0
  95
  96 #define PMB_BUS_SWITCH           1
  97 #define PMB_ADDR_SWITCH          (0 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
  98 #define PMB_ZONES_SWITCH         4
  99
 100 #define PMB_BUS_XRDP_RC0         1
 101 #define PMB_ADDR_XRDP_RC0        (17 | PMB_BUS_XRDP_RC0 << PMB_BUS_ID_SHIFT)
 102 #define PMB_ZONES_XRDP_RC0       1
 103
 104 #define PMB_BUS_XRDP_RC1         1
 105 #define PMB_ADDR_XRDP_RC1        (18 | PMB_BUS_XRDP_RC1 << PMB_BUS_ID_SHIFT)
 106 #define PMB_ZONES_XRDP_RC1       1
 107
 108 #define PMB_BUS_XRDP_RC2         1
 109 #define PMB_ADDR_XRDP_RC2        (19 | PMB_BUS_XRDP_RC2 << PMB_BUS_ID_SHIFT)
 110 #define PMB_ZONES_XRDP_RC2       1
 111
 112 #define PMB_BUS_XRDP_RC3         1
 113 #define PMB_ADDR_XRDP_RC3        (20 | PMB_BUS_XRDP_RC3 << PMB_BUS_ID_SHIFT)
 114 #define PMB_ZONES_XRDP_RC3       1
 115
 116 #define PMB_BUS_XRDP_RC4         1
 117 #define PMB_ADDR_XRDP_RC4        (21 | PMB_BUS_XRDP_RC4 << PMB_BUS_ID_SHIFT)
 118 #define PMB_ZONES_XRDP_RC4       1
 119
 120 #define PMB_BUS_XRDP_RC5         1
 121 #define PMB_ADDR_XRDP_RC5        (22 | PMB_BUS_XRDP_RC5 << PMB_BUS_ID_SHIFT)
 122 #define PMB_ZONES_XRDP_RC5       1
 123
 124 #define PMB_BUS_VDSL3_CORE       0
 125 #define PMB_ADDR_VDSL3_CORE      (23 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
 126 #define PMB_ZONES_VDSL3_CORE     1
 127
 128 #define PMB_BUS_VDSL3_MIPS       PMB_BUS_VDSL3_CORE
 129 #define PMB_ADDR_VDSL3_MIPS      PMB_ADDR_VDSL3_CORE
 130 #define PMB_ZONES_VDSL3_MIPS     PMB_ZONES_VDSL3_CORE
 131
 132 #define PMB_BUS_VDSL3_PMD        0
 133 #define PMB_ADDR_VDSL3_PMD       (24 | PMB_BUS_VDSL3_PMD << PMB_BUS_ID_SHIFT)
 134 #define PMB_ZONES_VDSL3_PMD      1
 135
 136 //--------- DGASP related bits/Offsets ------------------------
 137 #define BPCM_PHY_CNTL_OVERRIDE         0x08000000
 138 #define PMB_ADDR_VDSL_DGASP_PMD        PMB_ADDR_VDSL3_PMD
 139 #define BPCM_VDSL_PHY_CTL_REG          global_control   // Alias for register containing DGASP override inside the VDSL PMD
 140 #define BPCM_VDSL_AFE_CTL_REG          misc_control     // Alias for register containing DGASP configuration inside the VDSL PMD
 141
 142 #define PMB_BUS_CRYPTO           0
 143 #define PMB_ADDR_CRYPTO          (25 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
 144 #define PMB_ZONES_CRYPTO         1
 145
 146 #define AFEPLL_PMB_BUS_VDSL3_CORE       0
 147 #define AFEPLL_PMB_ADDR_VDSL3_CORE      (26 | AFEPLL_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
 148 #define AFEPLL_PMB_ZONES_VDSL3_CORE     0
 149
 150 #define PMB_BUS_ORION_CPU0       0
 151 #define PMB_ADDR_ORION_CPU0      (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
 152 #define PMB_ZONES_ORION_CPU0     1
 153
 154 #define PMB_BUS_ORION_CPU1       0
 155 #define PMB_ADDR_ORION_CPU1      (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
 156 #define PMB_ZONES_ORION_CPU1     1
 157
 158 #define PMB_BUS_ORION_CPU2       0
 159 #define PMB_ADDR_ORION_CPU2      (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
 160 #define PMB_ZONES_ORION_CPU2     1
 161
 162 #define PMB_BUS_ORION_CPU3       0
 163 #define PMB_ADDR_ORION_CPU3      (35 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT)
 164 #define PMB_ZONES_ORION_CPU3     1
 165
 166 #define PMB_BUS_ORION_NONCPU     0
 167 #define PMB_ADDR_ORION_NONCPU    (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
 168 #define PMB_ZONES_ORION_NONCPU   1
 169
 170 #define PMB_BUS_ORION_ARS        0
 171 #define PMB_ADDR_ORION_ARS       (37 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT)
 172 #define PMB_ZONES_ORION_ARS      0
 173
 174 #define PMB_BUS_BIU_PLL          0
 175 #define PMB_ADDR_BIU_PLL         (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
 176 #define PMB_ZONES_BIU_PLL        0
 177
 178 #define PMB_BUS_BIU_BPCM         0
 179 #define PMB_ADDR_BIU_BPCM        (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
 180 #define PMB_ZONES_BIU_BPCM       1
 181
 182 #define PMB_BUS_ORION_C0_ARS     0
 183 #define PMB_ADDR_ORION_C0_ARS    (45 | PMB_BUS_ORION_C0_ARS << PMB_BUS_ID_SHIFT)
 184 #define PMB_ZONES_ORION_C0_ARS   0
 185
 186 #define PMB_BUS_PCM              1
 187 #define PMB_ADDR_PCM             (3 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT)
 188 #define PMB_ZONES_PCM            4
 189
 190 enum {
 191         PCM_Zone_Main,
 192         PCM_Zone_PCM = 3
 193 };
 194 //--------- SOFT Reset bits for PCM ------------------------
 195 #define   BPCM_PCM_SRESET_PCM_N       0x00000040
 196
 197 #endif