in order for the option ephy-disable to work
without also needing ephy-base option,
we have to skip all the lines that write to mdio addresses that
assume those addresses do not have an external switch.
Otherwise, ephy ports will be disabled in hardware,
but register writes still happen as if they are enabled.
Split the functions so that other things are done first,
and ephy port setup can be skipped with a simple "return".
Tested on Engenius EPG600 (MT7620A ver:2 eco:3)
with QCA8337 external switch
Ref:
cc6fd6fbb505 ("ramips: mt7620: add ephy-disable option to switch driver")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
-static void mt7620_hw_init(struct mt7620_gsw *gsw)
+static void mt7620_ephy_init(struct mt7620_gsw *gsw)
{
u32 i;
u32 val;
u32 is_BGA = (rt_sysc_r32(SYSC_REG_CHIP_REV_ID) >> 16) & 1;
{
u32 i;
u32 val;
u32 is_BGA = (rt_sysc_r32(SYSC_REG_CHIP_REV_ID) >> 16) & 1;
- /* Internal ethernet requires PCIe RC mode */
- rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1);
-
- mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
-
- /* Enable MIB stats */
- mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
-
if (gsw->ephy_disable) {
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16) | (0x1f << 24),
GSW_REG_GPC1);
pr_info("gsw: internal ephy disabled\n");
if (gsw->ephy_disable) {
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16) | (0x1f << 24),
GSW_REG_GPC1);
pr_info("gsw: internal ephy disabled\n");
} else if (gsw->ephy_base) {
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16),
} else if (gsw->ephy_base) {
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16),
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);
- /* CPU Port6 Force Link 1G, FC ON */
- mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
-
- /* Set Port 6 as CPU Port */
- mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
-
/* setup port 4 */
if (gsw->port4_ephy) {
val = rt_sysc_r32(SYSC_REG_CFG1);
/* setup port 4 */
if (gsw->port4_ephy) {
val = rt_sysc_r32(SYSC_REG_CFG1);
+static void mt7620_mac_init(struct mt7620_gsw *gsw)
+{
+ /* Internal ethernet requires PCIe RC mode */
+ rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1);
+
+ /* Keep Global Clocks on Idle traffic */
+ mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
+
+ /* Set Port 6 to Force Link 1G, Flow Control ON */
+ mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
+
+ /* Set Port 6 as CPU Port */
+ mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
+
+ /* Enable MIB stats */
+ mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
+}
+
static const struct of_device_id mediatek_gsw_match[] = {
{ .compatible = "mediatek,mt7620-gsw" },
{},
static const struct of_device_id mediatek_gsw_match[] = {
{ .compatible = "mediatek,mt7620-gsw" },
{},
+ mt7620_mac_init(gsw);
+
+ mt7620_ephy_init(gsw);
if (gsw->irq) {
request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
if (gsw->irq) {
request_irq(gsw->irq, gsw_interrupt_mt7620, 0,