target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2020 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  * Author: Jianhui Zhao <zhaojh329@gmail.com>
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/phy/phy.h>
  11 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
  12 #include <dt-bindings/reset/mt7986-resets.h>
  13 #include <dt-bindings/pinctrl/mt65xx.h>
  14 #include <dt-bindings/leds/common.h>
  15 #include <dt-bindings/input/linux-event-codes.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/mux/mux.h>
  18
  19 / {
  20         compatible = "mediatek,mt7981";
  21         interrupt-parent = <&gic>;
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a53";
  32                         enable-method = "psci";
  33                         reg = <0x0>;
  34                 };
  35
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a53";
  39                         enable-method = "psci";
  40                         reg = <0x1>;
  41                 };
  42         };
  43
  44         pwm: pwm@10048000 {
  45                 compatible = "mediatek,mt7981-pwm";
  46                 reg = <0 0x10048000 0 0x1000>;
  47                 #pwm-cells = <2>;
  48                 clocks = <&infracfg CLK_INFRA_PWM_STA>,
  49                          <&infracfg CLK_INFRA_PWM_HCK>,
  50                          <&infracfg CLK_INFRA_PWM1_CK>,
  51                          <&infracfg CLK_INFRA_PWM2_CK>,
  52                          <&infracfg CLK_INFRA_PWM3_CK>;
  53                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
  54         };
  55
  56         fan: pwm-fan {
  57                 compatible = "pwm-fan";
  58                 /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */
  59                 cooling-levels = <0 128 192 255>;
  60                 #cooling-cells = <2>;
  61                 status = "disabled";
  62         };
  63
  64         thermal-zones {
  65                 cpu_thermal: cpu-thermal {
  66                         polling-delay-passive = <1000>;
  67                         polling-delay = <1000>;
  68                         thermal-sensors = <&thermal 0>;
  69                         trips {
  70                                 cpu_trip_crit: crit {
  71                                         temperature = <125000>;
  72                                         hysteresis = <2000>;
  73                                         type = "critical";
  74                                 };
  75
  76                                 cpu_trip_hot: hot {
  77                                         temperature = <120000>;
  78                                         hysteresis = <2000>;
  79                                         type = "hot";
  80                                 };
  81
  82                                 cpu_trip_active_high: active-high {
  83                                         temperature = <115000>;
  84                                         hysteresis = <2000>;
  85                                         type = "active";
  86                                 };
  87
  88                                 cpu_trip_active_med: active-med {
  89                                         temperature = <85000>;
  90                                         hysteresis = <2000>;
  91                                         type = "active";
  92                                 };
  93
  94                                 cpu_trip_active_low: active-low {
  95                                         temperature = <60000>;
  96                                         hysteresis = <2000>;
  97                                         type = "active";
  98                                 };
  99                         };
 100
 101                         cooling-maps {
 102                                 cpu-active-high {
 103                                         /* active: set fan to cooling level 3 */
 104                                         cooling-device = <&fan 3 3>;
 105                                         trip = <&cpu_trip_active_high>;
 106                                 };
 107
 108                                 cpu-active-med {
 109                                         /* active: set fan to cooling level 2 */
 110                                         cooling-device = <&fan 2 2>;
 111                                         trip = <&cpu_trip_active_med>;
 112                                 };
 113
 114                                 cpu-active-low {
 115                                         /* passive: set fan to cooling level 1 */
 116                                         cooling-device = <&fan 1 1>;
 117                                         trip = <&cpu_trip_active_low>;
 118                                 };
 119                         };
 120                 };
 121         };
 122
 123         thermal: thermal@1100c800 {
 124                 #thermal-sensor-cells = <1>;
 125                 compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
 126                 reg = <0 0x1100c800 0 0x800>;
 127                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 128                 clocks = <&infracfg CLK_INFRA_THERM_CK>,
 129                          <&infracfg CLK_INFRA_ADC_26M_CK>;
 130                 clock-names = "therm", "auxadc";
 131                 mediatek,auxadc = <&auxadc>;
 132                 mediatek,apmixedsys = <&apmixedsys>;
 133                 nvmem-cells = <&thermal_calibration>;
 134                 nvmem-cell-names = "calibration-data";
 135         };
 136
 137         auxadc: adc@1100d000 {
 138                 compatible = "mediatek,mt7981-auxadc",
 139                              "mediatek,mt7986-auxadc",
 140                              "mediatek,mt7622-auxadc";
 141                 reg = <0 0x1100d000 0 0x1000>;
 142                 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
 143                          <&infracfg CLK_INFRA_ADC_FRC_CK>;
 144                 clock-names = "main", "32k";
 145                 #io-channel-cells = <1>;
 146         };
 147
 148         wdma: wdma@15104800 {
 149                 compatible = "mediatek,wed-wdma";
 150                 reg = <0 0x15104800 0 0x400>,
 151                       <0 0x15104c00 0 0x400>;
 152         };
 153
 154         ap2woccif: ap2woccif@151a5000 {
 155                 compatible = "mediatek,ap2woccif";
 156                 reg = <0 0x151a5000 0 0x1000>,
 157                       <0 0x151ad000 0 0x1000>;
 158                 interrupt-parent = <&gic>;
 159                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
 161         };
 162
 163         reserved-memory {
 164                 #address-cells = <2>;
 165                 #size-cells = <2>;
 166                 ranges;
 167
 168                 /* 64 KiB reserved for ramoops/pstore */
 169                 ramoops@42ff0000 {
 170                         compatible = "ramoops";
 171                         reg = <0 0x42ff0000 0 0x10000>;
 172                         record-size = <0x1000>;
 173                 };
 174
 175                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 176                 secmon_reserved: secmon@43000000 {
 177                         reg = <0 0x43000000 0 0x30000>;
 178                         no-map;
 179                 };
 180
 181                 wmcpu_emi: wmcpu-reserved@47c80000 {
 182                         reg = <0 0x47c80000 0 0x100000>;
 183                         no-map;
 184                 };
 185
 186                 wo_emi0: wo-emi@47d80000 {
 187                         reg = <0 0x47d80000 0 0x40000>;
 188                         no-map;
 189                 };
 190
 191                 wo_data: wo-data@47dc0000 {
 192                         reg = <0 0x47dc0000 0 0x240000>;
 193                         no-map;
 194                 };
 195         };
 196
 197         psci {
 198                 compatible  = "arm,psci-0.2";
 199                 method      = "smc";
 200         };
 201
 202         trng {
 203                 compatible = "mediatek,mt7981-rng";
 204         };
 205
 206         clk40m: oscillator@0 {
 207                 compatible = "fixed-clock";
 208                 #clock-cells = <0>;
 209                 clock-frequency = <40000000>;
 210                 clock-output-names = "clkxtal";
 211         };
 212
 213         infracfg: infracfg@10001000 {
 214                 compatible = "mediatek,mt7981-infracfg", "syscon";
 215                 reg = <0 0x10001000 0 0x1000>;
 216                 #clock-cells = <1>;
 217         };
 218
 219         topckgen: topckgen@1001B000 {
 220                 compatible = "mediatek,mt7981-topckgen", "syscon";
 221                 reg = <0 0x1001B000 0 0x1000>;
 222                 #clock-cells = <1>;
 223         };
 224
 225         apmixedsys: apmixedsys@1001E000 {
 226                 compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
 227                 reg = <0 0x1001E000 0 0x1000>;
 228                 #clock-cells = <1>;
 229         };
 230
 231         timer {
 232                 compatible = "arm,armv8-timer";
 233                 interrupt-parent = <&gic>;
 234                 clock-frequency = <13000000>;
 235                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 236                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 237                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 238                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 239
 240         };
 241
 242         watchdog: watchdog@1001c000 {
 243                 compatible = "mediatek,mt7986-wdt",
 244                              "mediatek,mt6589-wdt";
 245                 reg = <0 0x1001c000 0 0x1000>;
 246                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 247                 #reset-cells = <1>;
 248                 status = "disabled";
 249         };
 250
 251         gic: interrupt-controller@c000000 {
 252                 compatible = "arm,gic-v3";
 253                 #interrupt-cells = <3>;
 254                 interrupt-parent = <&gic>;
 255                 interrupt-controller;
 256                 reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 257                       <0 0x0c080000 0 0x200000>; /* GICR */
 258
 259                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 260         };
 261
 262         uart0: serial@11002000 {
 263                 compatible = "mediatek,mt6577-uart";
 264                 reg = <0 0x11002000 0 0x400>;
 265                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 266                 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
 267                         <&infracfg CLK_INFRA_UART0_CK>;
 268                 clock-names = "baud", "bus";
 269                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 270                                   <&infracfg CLK_INFRA_UART0_SEL>;
 271                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 272                                          <&topckgen CLK_TOP_UART_SEL>;
 273                 pinctrl-0 = <&uart0_pins>;
 274                 pinctrl-names = "default";
 275                 status = "disabled";
 276         };
 277
 278         uart1: serial@11003000 {
 279                 compatible = "mediatek,mt6577-uart";
 280                 reg = <0 0x11003000 0 0x400>;
 281                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 282                 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
 283                         <&infracfg CLK_INFRA_UART1_CK>;
 284                 clock-names = "baud", "bus";
 285                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 286                                   <&infracfg CLK_INFRA_UART1_SEL>;
 287                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 288                                          <&topckgen CLK_TOP_UART_SEL>;
 289                 status = "disabled";
 290         };
 291
 292         uart2: serial@11004000 {
 293                 compatible = "mediatek,mt6577-uart";
 294                 reg = <0 0x11004000 0 0x400>;
 295                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 296                 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
 297                         <&infracfg CLK_INFRA_UART2_CK>;
 298                 clock-names = "baud", "bus";
 299                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 300                                   <&infracfg CLK_INFRA_UART2_SEL>;
 301                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 302                                          <&topckgen CLK_TOP_UART_SEL>;
 303                 status = "disabled";
 304         };
 305
 306         i2c0: i2c@11007000 {
 307                 compatible = "mediatek,mt7981-i2c";
 308                 reg = <0 0x11007000 0 0x1000>,
 309                       <0 0x10217080 0 0x80>;
 310                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 311                 clock-div = <1>;
 312                 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
 313                          <&infracfg CLK_INFRA_AP_DMA_CK>,
 314                          <&infracfg CLK_INFRA_I2C_MCK_CK>,
 315                          <&infracfg CLK_INFRA_I2C_PCK_CK>;
 316                 clock-names = "main", "dma", "arb", "pmic";
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319                 status = "disabled";
 320         };
 321
 322         pcie: pcie@11280000 {
 323                 compatible = "mediatek,mt7981-pcie",
 324                              "mediatek,mt7986-pcie";
 325                 device_type = "pci";
 326                 reg = <0 0x11280000 0 0x4000>;
 327                 reg-names = "pcie-mac";
 328                 #address-cells = <3>;
 329                 #size-cells = <2>;
 330                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 331                 bus-range = <0x00 0xff>;
 332                 ranges = <0x82000000 0 0x20000000
 333                           0x0 0x20000000 0 0x10000000>;
 334                 status = "disabled";
 335
 336                 clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
 337                          <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
 338                          <&infracfg CLK_INFRA_IPCIER_CK>,
 339                          <&infracfg CLK_INFRA_IPCIEB_CK>;
 340
 341                 phys = <&u3port0 PHY_TYPE_PCIE>;
 342                 phy-names = "pcie-phy";
 343
 344                 #interrupt-cells = <1>;
 345                 interrupt-map-mask = <0 0 0 7>;
 346                 interrupt-map = <0 0 0 1 &pcie_intc 0>,
 347                                 <0 0 0 2 &pcie_intc 1>,
 348                                 <0 0 0 3 &pcie_intc 2>,
 349                                 <0 0 0 4 &pcie_intc 3>;
 350                 pcie_intc: interrupt-controller {
 351                         interrupt-controller;
 352                         #address-cells = <0>;
 353                         #interrupt-cells = <1>;
 354                 };
 355         };
 356
 357         crypto: crypto@10320000 {
 358                 compatible = "inside-secure,safexcel-eip97";
 359                 reg = <0 0x10320000 0 0x40000>;
 360                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 361                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 362                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 363                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 364                 interrupt-names = "ring0", "ring1", "ring2", "ring3";
 365                 clocks = <&topckgen CLK_TOP_EIP97B>;
 366                 clock-names = "top_eip97_ck";
 367                 assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
 368                 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
 369         };
 370
 371         pio: pinctrl@11d00000 {
 372                 compatible = "mediatek,mt7981-pinctrl";
 373                 reg = <0 0x11d00000 0 0x1000>,
 374                       <0 0x11c00000 0 0x1000>,
 375                       <0 0x11c10000 0 0x1000>,
 376                       <0 0x11d20000 0 0x1000>,
 377                       <0 0x11e00000 0 0x1000>,
 378                       <0 0x11e20000 0 0x1000>,
 379                       <0 0x11f00000 0 0x1000>,
 380                       <0 0x11f10000 0 0x1000>,
 381                       <0 0x1000b000 0 0x1000>;
 382                 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
 383                             "iocfg_rb", "iocfg_lb", "iocfg_bl",
 384                             "iocfg_tm", "iocfg_tl", "eint";
 385                 gpio-controller;
 386                 #gpio-cells = <2>;
 387                 gpio-ranges = <&pio 0 0 56>;
 388                 interrupt-controller;
 389                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 390                 interrupt-parent = <&gic>;
 391                 #interrupt-cells = <2>;
 392
 393                 mdio_pins: mdc-mdio-pins {
 394                         mux {
 395                                 function = "eth";
 396                                 groups = "smi_mdc_mdio";
 397                         };
 398                 };
 399
 400                 uart0_pins: uart0-pins {
 401                         mux {
 402                                 function = "uart";
 403                                 groups = "uart0";
 404                         };
 405                 };
 406
 407                 wifi_dbdc_pins: wifi-dbdc-pins {
 408                         mux {
 409                                 function = "eth";
 410                                 groups = "wf0_mode1";
 411                         };
 412                         conf {
 413                                 pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
 414                                        "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
 415                                        "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
 416                                        "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
 417                                        "WF_CBA_RESETB", "WF_DIG_RESETB";
 418                                 drive-strength = <4>;
 419                         };
 420                 };
 421
 422                 gbe_led0_pins: gbe-led0-pins {
 423                         mux {
 424                                 function = "led";
 425                                 groups = "gbe_led0";
 426                         };
 427                 };
 428
 429                 gbe_led1_pins: gbe-led1-pins {
 430                         mux {
 431                                 function = "led";
 432                                 groups = "gbe_led1";
 433                         };
 434                 };
 435         };
 436
 437         ethsys: syscon@15000000 {
 438                 #address-cells = <1>;
 439                 #size-cells = <1>;
 440                 compatible = "mediatek,mt7981-ethsys",
 441                              "mediatek,mt7986-ethsys",
 442                              "syscon";
 443                 reg = <0 0x15000000 0 0x1000>;
 444                 #clock-cells = <1>;
 445                 #reset-cells = <1>;
 446         };
 447
 448         wed: wed@15010000 {
 449                 compatible = "mediatek,mt7981-wed",
 450                              "mediatek,mt7986-wed",
 451                              "syscon";
 452                 reg = <0 0x15010000 0 0x1000>;
 453                 interrupt-parent = <&gic>;
 454                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 455                 memory-region = <&wo_emi0>, <&wo_data>;
 456                 memory-region-names = "wo-emi", "wo-data";
 457                 mediatek,wo-ccif = <&wo_ccif0>;
 458                 mediatek,wo-ilm = <&wo_ilm0>;
 459                 mediatek,wo-dlm = <&wo_dlm0>;
 460                 mediatek,wo-cpuboot = <&wo_cpuboot>;
 461         };
 462
 463         eth: ethernet@15100000 {
 464                 compatible = "mediatek,mt7981-eth";
 465                 reg = <0 0x15100000 0 0x80000>;
 466                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 467                                 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 468                                 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 469                                 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 470                 clocks = <&ethsys CLK_ETH_FE_EN>,
 471                         <&ethsys CLK_ETH_GP2_EN>,
 472                         <&ethsys CLK_ETH_GP1_EN>,
 473                         <&ethsys CLK_ETH_WOCPU0_EN>,
 474                         <&sgmiisys0 CLK_SGM0_TX_EN>,
 475                         <&sgmiisys0 CLK_SGM0_RX_EN>,
 476                         <&sgmiisys0 CLK_SGM0_CK0_EN>,
 477                         <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
 478                         <&sgmiisys1 CLK_SGM1_TX_EN>,
 479                         <&sgmiisys1 CLK_SGM1_RX_EN>,
 480                         <&sgmiisys1 CLK_SGM1_CK1_EN>,
 481                         <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
 482                         <&topckgen CLK_TOP_SGM_REG>,
 483                         <&topckgen CLK_TOP_NETSYS_SEL>,
 484                         <&topckgen CLK_TOP_NETSYS_500M_SEL>;
 485                 clock-names = "fe", "gp2", "gp1", "wocpu0",
 486                                         "sgmii_tx250m", "sgmii_rx250m",
 487                                         "sgmii_cdr_ref", "sgmii_cdr_fb",
 488                                         "sgmii2_tx250m", "sgmii2_rx250m",
 489                                         "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 490                                         "sgmii_ck", "netsys0", "netsys1";
 491                 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
 492                                   <&topckgen CLK_TOP_SGM_325M_SEL>;
 493                 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
 494                                          <&topckgen CLK_TOP_CB_SGM_325M>;
 495                 mediatek,ethsys = <&ethsys>;
 496                 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
 497                 mediatek,infracfg = <&topmisc>;
 498                 mediatek,wed = <&wed>;
 499                 #reset-cells = <1>;
 500                 #address-cells = <1>;
 501                 #size-cells = <0>;
 502                 status = "disabled";
 503
 504                 mdio_bus: mdio-bus {
 505                         #address-cells = <1>;
 506                         #size-cells = <0>;
 507
 508                         int_gbe_phy: ethernet-phy@0 {
 509                                 reg = <0>;
 510                                 compatible = "ethernet-phy-ieee802.3-c22";
 511                                 phy-mode = "gmii";
 512                                 phy-is-integrated;
 513                                 nvmem-cells = <&phy_calibration>;
 514                                 nvmem-cell-names = "phy-cal-data";
 515
 516                                 leds {
 517                                         #address-cells = <1>;
 518                                         #size-cells = <0>;
 519
 520                                         int_gbe_phy_led0: int-gbe-phy-led0@0 {
 521                                                 reg = <0>;
 522                                                 function = LED_FUNCTION_LAN;
 523                                                 status = "disabled";
 524                                         };
 525
 526                                         int_gbe_phy_led1: int-gbe-phy-led1@1 {
 527                                                 reg = <1>;
 528                                                 function = LED_FUNCTION_LAN;
 529                                                 status = "disabled";
 530                                         };
 531                                 };
 532                         };
 533                 };
 534         };
 535
 536         wo_dlm0: syscon@151e8000 {
 537                 compatible = "mediatek,mt7986-wo-dlm", "syscon";
 538                 reg = <0 0x151e8000 0 0x2000>;
 539         };
 540
 541         wo_ilm0: syscon@151e0000 {
 542                 compatible = "mediatek,mt7986-wo-ilm", "syscon";
 543                 reg = <0 0x151e0000 0 0x8000>;
 544         };
 545
 546         wo_cpuboot: syscon@15194000 {
 547                 compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
 548                 reg = <0 0x15194000 0 0x1000>;
 549         };
 550
 551         wo_ccif0: syscon@151a5000 {
 552                 compatible = "mediatek,mt7986-wo-ccif", "syscon";
 553                 reg = <0 0x151a5000 0 0x1000>;
 554                 interrupt-parent = <&gic>;
 555                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 556         };
 557
 558         sgmiisys0: syscon@10060000 {
 559                 compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
 560                 reg = <0 0x10060000 0 0x1000>;
 561                 mediatek,pnswap;
 562                 #clock-cells = <1>;
 563         };
 564
 565         sgmiisys1: syscon@10070000 {
 566                 compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
 567                 reg = <0 0x10070000 0 0x1000>;
 568                 #clock-cells = <1>;
 569         };
 570
 571         topmisc: topmisc@11d10000 {
 572                 compatible = "mediatek,mt7981-topmisc", "syscon";
 573                 reg = <0 0x11d10000 0 0x10000>;
 574                 #clock-cells = <1>;
 575         };
 576
 577         snand: snfi@11005000 {
 578                 compatible = "mediatek,mt7986-snand";
 579                 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
 580                 reg-names = "nfi", "ecc";
 581                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 582                 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
 583                          <&infracfg CLK_INFRA_NFI1_CK>,
 584                          <&infracfg CLK_INFRA_NFI_HCK_CK>;
 585                 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
 586                 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
 587                                   <&topckgen CLK_TOP_NFI1X_SEL>;
 588                 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
 589                                          <&topckgen CLK_TOP_CB_M_D8>;
 590                 #address-cells = <1>;
 591                 #size-cells = <0>;
 592                 status = "disabled";
 593         };
 594
 595         mmc0: mmc@11230000 {
 596                 compatible = "mediatek,mt7986-mmc",
 597                                         "mediatek,mt7981-mmc";
 598                 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
 599                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 600                 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
 601                          <&infracfg CLK_INFRA_MSDC_HCK_CK>,
 602                          <&infracfg CLK_INFRA_MSDC_66M_CK>,
 603                          <&infracfg CLK_INFRA_MSDC_133M_CK>;
 604                 assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
 605                                   <&topckgen CLK_TOP_EMMC_400M_SEL>;
 606                 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
 607                                          <&topckgen CLK_TOP_CB_NET2_D2>;
 608                 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
 609                 status = "disabled";
 610         };
 611
 612         wed_pcie: wed_pcie@10003000 {
 613                 compatible = "mediatek,wed_pcie";
 614                 reg = <0 0x10003000 0 0x10>;
 615         };
 616
 617         spi0: spi@1100a000 {
 618                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 619                 #address-cells = <1>;
 620                 #size-cells = <0>;
 621                 reg = <0 0x1100a000 0 0x100>;
 622                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 623                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 624                          <&topckgen CLK_TOP_SPI_SEL>,
 625                          <&infracfg CLK_INFRA_SPI0_CK>,
 626                          <&infracfg CLK_INFRA_SPI0_HCK_CK>;
 627
 628                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 629                 status = "disabled";
 630         };
 631
 632         spi1: spi@1100b000 {
 633                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 634                 #address-cells = <1>;
 635                 #size-cells = <0>;
 636                 reg = <0 0x1100b000 0 0x100>;
 637                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 638                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 639                          <&topckgen CLK_TOP_SPIM_MST_SEL>,
 640                          <&infracfg CLK_INFRA_SPI1_CK>,
 641                          <&infracfg CLK_INFRA_SPI1_HCK_CK>;
 642                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 643                 status = "disabled";
 644         };
 645
 646         spi2: spi@11009000 {
 647                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 648                 #address-cells = <1>;
 649                 #size-cells = <0>;
 650                 reg = <0 0x11009000 0 0x100>;
 651                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 652                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 653                          <&topckgen CLK_TOP_SPI_SEL>,
 654                          <&infracfg CLK_INFRA_SPI2_CK>,
 655                          <&infracfg CLK_INFRA_SPI2_HCK_CK>;
 656                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 657                 status = "disabled";
 658         };
 659
 660         consys: consys@10000000 {
 661                 compatible = "mediatek,mt7981-consys";
 662                 reg = <0 0x10000000 0 0x8600000>;
 663                 memory-region = <&wmcpu_emi>;
 664         };
 665
 666         xhci: usb@11200000 {
 667                 compatible = "mediatek,mt7986-xhci",
 668                              "mediatek,mtk-xhci";
 669                 reg = <0 0x11200000 0 0x2e00>,
 670                       <0 0x11203e00 0 0x0100>;
 671                 reg-names = "mac", "ippc";
 672                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 673                 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
 674                          <&infracfg CLK_INFRA_IUSB_CK>,
 675                          <&infracfg CLK_INFRA_IUSB_133_CK>,
 676                          <&infracfg CLK_INFRA_IUSB_66M_CK>,
 677                          <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
 678                 clock-names = "sys_ck",
 679                               "ref_ck",
 680                               "mcu_ck",
 681                               "dma_ck",
 682                               "xhci_ck";
 683                 phys = <&u2port0 PHY_TYPE_USB2>,
 684                        <&u3port0 PHY_TYPE_USB3>;
 685                 vusb33-supply = <&reg_3p3v>;
 686                 status = "disabled";
 687         };
 688
 689         usb_phy: usb-phy@11e10000 {
 690                 compatible = "mediatek,mt7981",
 691                              "mediatek,generic-tphy-v2";
 692                 #address-cells = <1>;
 693                 #size-cells = <1>;
 694                 ranges = <0 0 0x11e10000 0x1700>;
 695                 status = "disabled";
 696
 697                 u2port0: usb-phy@0 {
 698                         reg = <0x0 0x700>;
 699                         clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
 700                         clock-names = "ref";
 701                         #phy-cells = <1>;
 702                 };
 703
 704                 u3port0: usb-phy@700 {
 705                         reg = <0x700 0x900>;
 706                         clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
 707                         clock-names = "ref";
 708                         #phy-cells = <1>;
 709                         mediatek,syscon-type = <&topmisc 0x218 0>;
 710                         status = "okay";
 711                 };
 712         };
 713
 714         reg_3p3v: regulator-3p3v {
 715                 compatible = "regulator-fixed";
 716                 regulator-name = "fixed-3.3V";
 717                 regulator-min-microvolt = <3300000>;
 718                 regulator-max-microvolt = <3300000>;
 719                 regulator-boot-on;
 720                 regulator-always-on;
 721         };
 722
 723         efuse: efuse@11f20000 {
 724                 compatible = "mediatek,mt7981-efuse",
 725                              "mediatek,efuse";
 726                 reg = <0 0x11f20000 0 0x1000>;
 727                 #address-cells = <1>;
 728                 #size-cells = <1>;
 729                 status = "okay";
 730
 731                 thermal_calibration: thermal-calib@274 {
 732                         reg = <0x274 0xc>;
 733                 };
 734
 735                 phy_calibration: phy-calib@8dc {
 736                         reg = <0x8dc 0x10>;
 737                 };
 738
 739                 comb_rx_imp_p0: usb3-rx-imp@8c8 {
 740                         reg = <0x8c8 1>;
 741                         bits = <0 5>;
 742                 };
 743
 744                 comb_tx_imp_p0: usb3-tx-imp@8c8 {
 745                         reg = <0x8c8 2>;
 746                         bits = <5 5>;
 747                 };
 748
 749                 comb_intr_p0: usb3-intr@8c9 {
 750                         reg = <0x8c9 1>;
 751                         bits = <2 6>;
 752                 };
 753         };
 754
 755         afe: audio-controller@11210000 {
 756                 compatible = "mediatek,mt79xx-audio";
 757                 reg = <0 0x11210000 0 0x9000>;
 758                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 759                 clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
 760                          <&infracfg CLK_INFRA_AUD_26M_CK>,
 761                          <&infracfg CLK_INFRA_AUD_L_CK>,
 762                          <&infracfg CLK_INFRA_AUD_AUD_CK>,
 763                          <&infracfg CLK_INFRA_AUD_EG2_CK>,
 764                          <&topckgen CLK_TOP_AUD_SEL>;
 765                 clock-names = "aud_bus_ck",
 766                               "aud_26m_ck",
 767                               "aud_l_ck",
 768                               "aud_aud_ck",
 769                               "aud_eg2_ck",
 770                               "aud_sel";
 771                 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
 772                                   <&topckgen CLK_TOP_A1SYS_SEL>,
 773                                   <&topckgen CLK_TOP_AUD_L_SEL>,
 774                                   <&topckgen CLK_TOP_A_TUNER_SEL>;
 775                 assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
 776                                          <&topckgen CLK_TOP_APLL2_D4>,
 777                                          <&topckgen CLK_TOP_CB_APLL2_196M>,
 778                                          <&topckgen CLK_TOP_APLL2_D4>;
 779                 status = "disabled";
 780         };
 781
 782         ice: ice_debug {
 783                 compatible = "mediatek,mt7981-ice_debug",
 784                            "mediatek,mt2701-ice_debug";
 785                 clocks = <&infracfg CLK_INFRA_DBG_CK>;
 786                 clock-names = "ice_dbg";
 787         };
 788
 789         wifi: wifi@18000000 {
 790                 compatible = "mediatek,mt7981-wmac";
 791                 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
 792                 reset-names = "consys";
 793                 pinctrl-0 = <&wifi_dbdc_pins>;
 794                 pinctrl-names = "dbdc";
 795                 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
 796                          <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
 797                 clock-names = "mcu", "ap2conn";
 798                 reg = <0 0x18000000 0 0x1000000>,
 799                       <0 0x10003000 0 0x1000>,
 800                       <0 0x11d10000 0 0x1000>;
 801                 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 802                              <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 803                              <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 804                              <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 805                 memory-region = <&wmcpu_emi>;
 806                 status = "disabled";
 807         };
 808 };