2 # Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
4 # SPDX-License-Identifier: BSD-3-Clause
7 # Use the GICv3 driver on the FVP by default
8 FVP_USE_GIC_DRIVER
:= FVP_GICV3
10 # Use the SP804 timer instead of the generic one
11 FVP_USE_SP804_TIMER
:= 0
13 # Default cluster count for FVP
14 FVP_CLUSTER_COUNT
:= 2
16 # Default number of CPUs per cluster on FVP
17 FVP_MAX_CPUS_PER_CLUSTER
:= 4
19 # Default number of threads per CPU on FVP
20 FVP_MAX_PE_PER_CPU
:= 1
22 FVP_DT_PREFIX
:= fvp-base-gicv3-psci
24 $(eval
$(call assert_boolean
,FVP_USE_SP804_TIMER
))
25 $(eval
$(call add_define
,FVP_USE_SP804_TIMER
))
27 # The FVP platform depends on this macro to build with correct GIC driver.
28 $(eval
$(call add_define
,FVP_USE_GIC_DRIVER
))
30 # Pass FVP_CLUSTER_COUNT to the build system.
31 $(eval
$(call add_define
,FVP_CLUSTER_COUNT
))
33 # Pass FVP_MAX_CPUS_PER_CLUSTER to the build system.
34 $(eval
$(call add_define
,FVP_MAX_CPUS_PER_CLUSTER
))
36 # Pass FVP_MAX_PE_PER_CPU to the build system.
37 $(eval
$(call add_define
,FVP_MAX_PE_PER_CPU
))
39 # Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2,
40 # choose the CCI driver , else the CCN driver
41 ifeq ($(FVP_CLUSTER_COUNT
), 0)
42 $(error
"Incorrect cluster count specified for FVP port")
43 else ifeq ($(FVP_CLUSTER_COUNT
),$(filter $(FVP_CLUSTER_COUNT
),1 2))
44 FVP_INTERCONNECT_DRIVER
:= FVP_CCI
46 FVP_INTERCONNECT_DRIVER
:= FVP_CCN
49 $(eval
$(call add_define
,FVP_INTERCONNECT_DRIVER
))
51 FVP_GICV3_SOURCES
:= drivers
/arm
/gic
/common
/gic_common.c \
52 drivers
/arm
/gic
/v3
/gicv3_main.c \
53 drivers
/arm
/gic
/v3
/gicv3_helpers.c \
54 plat
/common
/plat_gicv3.c \
55 plat
/arm
/common
/arm_gicv3.c
57 # Choose the GIC sources depending upon the how the FVP will be invoked
58 ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3
)
59 FVP_GIC_SOURCES
:= ${FVP_GICV3_SOURCES} \
60 drivers
/arm
/gic
/v3
/gic500.c
61 else ifeq (${FVP_USE_GIC_DRIVER},FVP_GIC600
)
62 FVP_GIC_SOURCES
:= ${FVP_GICV3_SOURCES} \
63 drivers
/arm
/gic
/v3
/gic600.c
64 else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2
)
65 FVP_GIC_SOURCES
:= drivers
/arm
/gic
/common
/gic_common.c \
66 drivers
/arm
/gic
/v2
/gicv2_main.c \
67 drivers
/arm
/gic
/v2
/gicv2_helpers.c \
68 plat
/common
/plat_gicv2.c \
69 plat
/arm
/common
/arm_gicv2.c
71 FVP_DT_PREFIX
:= fvp-base-gicv2-psci
73 $(error
"Incorrect GIC driver chosen on FVP port")
76 ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI
)
77 FVP_INTERCONNECT_SOURCES
:= drivers
/arm
/cci
/cci.c
78 else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN
)
79 FVP_INTERCONNECT_SOURCES
:= drivers
/arm
/ccn
/ccn.c \
80 plat
/arm
/common
/arm_ccn.c
82 $(error
"Incorrect CCN driver chosen on FVP port")
85 FVP_SECURITY_SOURCES
:= drivers
/arm
/tzc
/tzc400.c \
86 plat
/arm
/board
/fvp
/fvp_security.c \
87 plat
/arm
/common
/arm_tzc400.c
90 PLAT_INCLUDES
:= -Iplat
/arm
/board
/fvp
/include
93 PLAT_BL_COMMON_SOURCES
:= plat
/arm
/board
/fvp
/fvp_common.c
95 FVP_CPU_LIBS
:= lib
/cpus
/${ARCH}/aem_generic.S
97 ifeq (${ARCH}, aarch64
)
99 # select a different set of CPU files, depending on whether we compile for
100 # hardware assisted coherency cores or not
101 ifeq (${HW_ASSISTED_COHERENCY}, 0)
102 # Cores used without DSU
103 FVP_CPU_LIBS
+= lib
/cpus
/aarch64
/cortex_a35.S \
104 lib
/cpus
/aarch64
/cortex_a53.S \
105 lib
/cpus
/aarch64
/cortex_a57.S \
106 lib
/cpus
/aarch64
/cortex_a72.S \
107 lib
/cpus
/aarch64
/cortex_a73.S
109 # Cores used with DSU only
110 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
112 FVP_CPU_LIBS
+= lib
/cpus
/aarch64
/cortex_a76.S \
113 lib
/cpus
/aarch64
/cortex_a76ae.S \
114 lib
/cpus
/aarch64
/cortex_a77.S \
115 lib
/cpus
/aarch64
/neoverse_n1.S \
116 lib
/cpus
/aarch64
/neoverse_e1.S \
117 lib
/cpus
/aarch64
/neoverse_zeus.S \
118 lib
/cpus
/aarch64
/cortex_hercules.S \
119 lib
/cpus
/aarch64
/cortex_hercules_ae.S \
120 lib
/cpus
/aarch64
/cortex_a65.S
122 # AArch64/AArch32 cores
123 FVP_CPU_LIBS
+= lib
/cpus
/aarch64
/cortex_a55.S \
124 lib
/cpus
/aarch64
/cortex_a75.S
128 FVP_CPU_LIBS
+= lib
/cpus
/aarch32
/cortex_a32.S
131 BL1_SOURCES
+= drivers
/arm
/smmu
/smmu_v3.c \
132 drivers
/arm
/sp805
/sp805.c \
133 drivers
/delay_timer
/delay_timer.c \
134 drivers
/io
/io_semihosting.c \
135 lib
/semihosting
/semihosting.c \
136 lib
/semihosting
/${ARCH}/semihosting_call.S \
137 plat
/arm
/board
/fvp
/${ARCH}/fvp_helpers.S \
138 plat
/arm
/board
/fvp
/fvp_bl1_setup.c \
139 plat
/arm
/board
/fvp
/fvp_err.c \
140 plat
/arm
/board
/fvp
/fvp_io_storage.c \
141 plat
/arm
/board
/fvp
/fvp_trusted_boot.c \
143 ${FVP_INTERCONNECT_SOURCES}
145 ifeq (${FVP_USE_SP804_TIMER},1)
146 BL1_SOURCES
+= drivers
/arm
/sp804
/sp804_delay_timer.c
148 BL1_SOURCES
+= drivers
/delay_timer
/generic_delay_timer.c
152 BL2_SOURCES
+= drivers
/arm
/sp805
/sp805.c \
153 drivers
/io
/io_semihosting.c \
154 lib
/utils
/mem_region.c \
155 lib
/semihosting
/semihosting.c \
156 lib
/semihosting
/${ARCH}/semihosting_call.S \
157 plat
/arm
/board
/fvp
/fvp_bl2_setup.c \
158 plat
/arm
/board
/fvp
/fvp_err.c \
159 plat
/arm
/board
/fvp
/fvp_io_storage.c \
160 plat
/arm
/board
/fvp
/fvp_trusted_boot.c \
161 plat
/arm
/common
/arm_nor_psci_mem_protect.c \
162 ${FVP_SECURITY_SOURCES}
166 ifeq (${BL2_AT_EL3},1)
167 BL2_SOURCES
+= plat
/arm
/board
/fvp
/${ARCH}/fvp_helpers.S \
168 plat
/arm
/board
/fvp
/fvp_bl2_el3_setup.c \
170 ${FVP_INTERCONNECT_SOURCES}
173 ifeq (${FVP_USE_SP804_TIMER},1)
174 BL2_SOURCES
+= drivers
/arm
/sp804
/sp804_delay_timer.c
177 BL2U_SOURCES
+= plat
/arm
/board
/fvp
/fvp_bl2u_setup.c \
178 ${FVP_SECURITY_SOURCES}
180 ifeq (${FVP_USE_SP804_TIMER},1)
181 BL2U_SOURCES
+= drivers
/arm
/sp804
/sp804_delay_timer.c
184 BL31_SOURCES
+= drivers
/arm
/fvp
/fvp_pwrc.c \
185 drivers
/arm
/smmu
/smmu_v3.c \
186 drivers
/delay_timer
/delay_timer.c \
187 drivers
/cfi
/v2m
/v2m_flash.c \
188 lib
/utils
/mem_region.c \
189 plat
/arm
/board
/fvp
/fvp_bl31_setup.c \
190 plat
/arm
/board
/fvp
/fvp_pm.c \
191 plat
/arm
/board
/fvp
/fvp_topology.c \
192 plat
/arm
/board
/fvp
/aarch64
/fvp_helpers.S \
193 plat
/arm
/common
/arm_nor_psci_mem_protect.c \
196 ${FVP_INTERCONNECT_SOURCES} \
197 ${FVP_SECURITY_SOURCES}
199 ifeq (${FVP_USE_SP804_TIMER},1)
200 BL31_SOURCES
+= drivers
/arm
/sp804
/sp804_delay_timer.c
202 BL31_SOURCES
+= drivers
/delay_timer
/generic_delay_timer.c
205 # Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
207 FVP_HW_CONFIG_DTS
:= fdts
/${FVP_DT_PREFIX}.dts
208 FDT_SOURCES
+= $(addprefix plat
/arm
/board
/fvp
/fdts
/, \
209 ${PLAT}_tb_fw_config.dts \
210 ${PLAT}_soc_fw_config.dts \
211 ${PLAT}_nt_fw_config.dts \
214 FVP_TB_FW_CONFIG
:= ${BUILD_PLAT}/fdts
/${PLAT}_tb_fw_config.dtb
215 FVP_SOC_FW_CONFIG
:= ${BUILD_PLAT}/fdts
/${PLAT}_soc_fw_config.dtb
216 FVP_NT_FW_CONFIG
:= ${BUILD_PLAT}/fdts
/${PLAT}_nt_fw_config.dtb
219 FDT_SOURCES
+= plat
/arm
/board
/fvp
/fdts
/${PLAT}_tsp_fw_config.dts
220 FVP_TOS_FW_CONFIG
:= ${BUILD_PLAT}/fdts
/${PLAT}_tsp_fw_config.dtb
222 # Add the TOS_FW_CONFIG to FIP and specify the same to certtool
223 $(eval
$(call TOOL_ADD_PAYLOAD
,${FVP_TOS_FW_CONFIG},--tos-fw-config
))
226 # Add the TB_FW_CONFIG to FIP and specify the same to certtool
227 $(eval
$(call TOOL_ADD_PAYLOAD
,${FVP_TB_FW_CONFIG},--tb-fw-config
))
228 # Add the SOC_FW_CONFIG to FIP and specify the same to certtool
229 $(eval
$(call TOOL_ADD_PAYLOAD
,${FVP_SOC_FW_CONFIG},--soc-fw-config
))
230 # Add the NT_FW_CONFIG to FIP and specify the same to certtool
231 $(eval
$(call TOOL_ADD_PAYLOAD
,${FVP_NT_FW_CONFIG},--nt-fw-config
))
233 FDT_SOURCES
+= ${FVP_HW_CONFIG_DTS}
234 $(eval FVP_HW_CONFIG
:= ${BUILD_PLAT}/$(patsubst %.dts
,%.dtb
,$(FVP_HW_CONFIG_DTS
)))
236 # Add the HW_CONFIG to FIP and specify the same to certtool
237 $(eval
$(call TOOL_ADD_PAYLOAD
,${FVP_HW_CONFIG},--hw-config
))
240 # Enable Activity Monitor Unit extensions by default
243 # Enable dynamic mitigation support by default
244 DYNAMIC_WORKAROUND_CVE_2018_3639
:= 1
246 ifneq (${RESET_TO_BL31},1)
247 # Enable reclaiming of BL31 initialisation code for secondary cores stacks for
248 # FVP. We cannot enable PIE for this case because the overlayed init section
249 # creates some dynamic relocations which cannot be handled by the fixup
251 RECLAIM_INIT_CODE
:= 1
253 # Enable PIE support when RESET_TO_BL31=1
257 ifeq (${ENABLE_AMU},1)
258 BL31_SOURCES
+= lib
/cpus
/aarch64
/cpuamu.c \
259 lib
/cpus
/aarch64
/cpuamu_helpers.S
261 ifeq (${HW_ASSISTED_COHERENCY}, 1)
262 BL31_SOURCES
+= lib
/cpus
/aarch64
/cortex_a75_pubsub.c \
263 lib
/cpus
/aarch64
/neoverse_n1_pubsub.c
267 ifeq (${RAS_EXTENSION},1)
268 BL31_SOURCES
+= plat
/arm
/board
/fvp
/aarch64
/fvp_ras.c
271 ifneq (${ENABLE_STACK_PROTECTOR},0)
272 PLAT_BL_COMMON_SOURCES
+= plat
/arm
/board
/fvp
/fvp_stack_protector.c
275 ifeq (${ARCH},aarch32
)
279 # Enable the dynamic translation tables library.
280 ifeq (${ARCH},aarch32
)
281 ifeq (${RESET_TO_SP_MIN},1)
282 BL32_CFLAGS
+= -DPLAT_XLAT_TABLES_DYNAMIC
=1
285 ifeq (${RESET_TO_BL31},1)
286 BL31_CFLAGS
+= -DPLAT_XLAT_TABLES_DYNAMIC
=1
288 ifeq (${ENABLE_SPM},1)
290 BL31_CFLAGS
+= -DPLAT_XLAT_TABLES_DYNAMIC
=1
294 BL31_CFLAGS
+= -DPLAT_XLAT_TABLES_DYNAMIC
=1
298 # Add support for platform supplied linker script for BL31 build
299 $(eval
$(call add_define
,PLAT_EXTRA_LD_SCRIPT
))
301 ifneq (${BL2_AT_EL3}, 0)
302 override BL1_SOURCES
=
305 include plat
/arm
/board
/common
/board_common.mk
306 include plat
/arm
/common
/arm_common.mk
308 # FVP being a development platform, enable capability to disable Authentication
309 # dynamically if TRUSTED_BOARD_BOOT is set.
310 ifeq (${TRUSTED_BOARD_BOOT}, 1)
311 DYN_DISABLE_AUTH
:= 1