lib/cpus/aarch64/cortex_a65.S

   1 /*
   2  * Copyright (c) 2019, Arm Limited. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6 #include <arch.h>
   7
   8 #include <asm_macros.S>
   9 #include <common/bl_common.h>
  10 #include <common/debug.h>
  11 #include <cortex_a65.h>
  12 #include <cpu_macros.S>
  13 #include <plat_macros.S>
  14
  15 /* Hardware handled coherency */
  16 #if !HW_ASSISTED_COHERENCY
  17 #error "Cortex-A65 must be compiled with HW_ASSISTED_COHERENCY enabled"
  18 #endif
  19
  20 /* 64-bit only core */
  21 #if CTX_INCLUDE_AARCH32_REGS
  22 #error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
  23 #endif
  24
  25 /* -------------------------------------------------
  26  * The CPU Ops reset function for Cortex-A65.
  27  * Shall clobber: x0-x19
  28  * -------------------------------------------------
  29  */
  30 func cortex_a65_reset_func
  31         mov     x19, x30
  32
  33 #if ERRATA_DSU_936184
  34         bl      errata_dsu_936184_wa
  35 #endif
  36
  37         ret     x19
  38 endfunc cortex_a65_reset_func
  39
  40 func cortex_a65_cpu_pwr_dwn
  41         mrs     x0, CORTEX_A65_CPUPWRCTLR_EL1
  42         orr     x0, x0, #CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
  43         msr     CORTEX_A65_CPUPWRCTLR_EL1, x0
  44         isb
  45         ret
  46 endfunc cortex_a65_cpu_pwr_dwn
  47
  48 #if REPORT_ERRATA
  49 /*
  50  * Errata printing function for Cortex-A65. Must follow AAPCS.
  51  */
  52 func cortex_a65_errata_report
  53         stp     x8, x30, [sp, #-16]!
  54
  55         bl      cpu_get_rev_var
  56         mov     x8, x0
  57
  58         /*
  59          * Report all errata. The revision-variant information is passed to
  60          * checking functions of each errata.
  61          */
  62         report_errata ERRATA_DSU_936184, cortex_a65, dsu_936184
  63
  64         ldp     x8, x30, [sp], #16
  65         ret
  66 endfunc cortex_a65_errata_report
  67 #endif
  68
  69 .section .rodata.cortex_a65_regs, "aS"
  70 cortex_a65_regs:  /* The ascii list of register names to be reported */
  71         .asciz  "cpuectlr_el1", ""
  72
  73 func cortex_a65_cpu_reg_dump
  74         adr     x6, cortex_a65_regs
  75         mrs     x8, CORTEX_A65_ECTLR_EL1
  76         ret
  77 endfunc cortex_a65_cpu_reg_dump
  78
  79 declare_cpu_ops cortex_a65, CORTEX_A65_MIDR, \
  80         cortex_a65_reset_func, \
  81         cortex_a65_cpu_pwr_dwn